AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet
AD9683-170EBZ
Specifications of AD9683-170EBZ
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AD9683-170EBZ Summary of contents
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... CMOS DIGITAL CONTROL INPUT REGISTERS CLOCK GENERATION CMOS CMOS DIGITAL FAST DIGITAL DETECT INPUT/OUTPUT OUTPUT SDIO SCLK CS RST Figure 14-bit ADC with sampling speeds AD9683 is designed to support communications ©2013 Analog Devices, Inc. All rights reserved. www.analog.com SERDOUT0± PDWN FD ...
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... AD9683 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ............................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 Equivalent Circuits ......................................................................... 18 Theory of Operation ...
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... MHz. 6. Operation from a single 1.8 V power supply. 7. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrangefast detection, and serial output configuration. Rev Page AD9683 ...
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... Rev Page Data Sheet AD9683-250 Typ Max Unit Bits Guaranteed ±9 mV −5.3/+1.2 %FSR ±0.75 LSB ±0.5 LSB ±2.7 LSB ±1.5 LSB ±7 ppm/°C ±39 ppm/°C 1.42 LSB rms 1.75 V p-p 2 kΩ ...
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... Full −81 25°C −94 25°C −89 Full 25°C −87 25°C −99 25°C −92 Full −83 25°C −96 25°C −94 Full 25°C −95 Rev Page AD9683 AD9683-250 Min Typ Max Unit 72.1 dBFS 71.7 dBFS dBFS 71.3 dBFS 70.6 dBFS 70.0 dBFS 70.0 dBFS 70.9 dBFS 70.6 dBFS dBFS 70.1 dBFS 69 ...
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... Full AGND Full 0 Full −150 Full Full 8 Full Full 0.3 Full DGND Full 0.9 Full −5 Full −10 Full Full 12 Rev Page Data Sheet AD9683-250 Min Typ Max Unit 87 dBc 1000 MHz Typ Max Unit 625 MHz 0.9 V 3.6 V p-p AVDD V 1.4 V +60 µA 0 µA ...
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... Full 45 Full −10 Full Full Full 1.22 Full 0 Full 45 Full −10 Full Full Full 400 Full 0.75 Full 1.79 Full 1.75 Full 1.6 Full Full Full Rev Page AD9683 Typ Max Unit LVDS 0.9 V 3.6 V p-p AVDD V 1 µA +10 µ kΩ 2 µA −45 µA 26 kΩ ...
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... Full J Full 25°C 25°C t 25°C LOCK 25°C 25°C 25°C Full Full Full Full Full Full Full Full Full 25°C Full Rev Page Data Sheet AD9683-170 AD9683-250 Min Typ Max Min Typ Max 40 170 40 250 300 300 40 40 400 400 0 0 2.61 2.9 3.19 1.8 2.0 2.2 2 ...
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... Time required after hard or soft reset until SPI access is available (not shown in figures) SAMPLE – 1 SAMPLE N – 35 ENCODED INTO 2 8B/10B SYMBOLS Figure 2. Data Output Timing t REFSRF t REFHRF Rev Page AD9683 Min Typ Max Unit ...
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... AD9683 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to DRGND DVDD to DGND VIN+, VIN− to AGND CLK+, CLK− to AGND RFCLK to AGND VCM to AGND CS, PDWN to DGND SCLK to DGND SDIO to DGND RST to DGND FD to DGND SERDOUT0+, SERDOUT0− to AGND SYNCINB+, SYNCINB− to DGND SYSREF+, SYSREF− ...
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... Fast Detect Indicator (CMOS Levels). Input JESD204B LVDS SYSREF Input—True. Input JESD204B LVDS SYSREF Input—Complement. Input JESD204B LVDS Sync Input—True. Input JESD204B LVDS Sync Input—Complement. Output CML Output Data—Complement. Output CML Output Data—True. Rev Page AD9683 ...
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... AD9683 Pin No. Mnemonic Device Under Test (DUT) Controls 8 RST 20 SDIO 21 SCLK PDWN Type Description Input Digital Reset (Active Low). Input/output SPI Serial Data I/O. Input SPI Serial Clock. Input SPI Chip Select (Active Low). This pin needs an external pull-up. Input Power-Down Input (Active High). The operation of this pin depends on SPI mode and can be configured as power-down or standby (see Table 17) ...
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... Figure 9. AD9683-170 Single-Tone FFT with f 120 100 –100 = 185.1 MHz Figure 10. AD9683-170 Single-Tone SNR/SFDR vs. Input Amplitude (A IN Rev Page 170MSPS 185.1MHz AT –1dBFS SNR = 70.1dB (71.1dBFS) SFDR = 84dBc THIRD HARMONIC SECOND HARMONIC ...
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... INPUT AMPLITUDE (dBFS) Figure 13. AD9683-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 89.12 MHz 92.12 MHz, f IN1 IN2 –20 –40 –60 –80 –100 –120 ) Figure 14. AD9683-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN –100 –120 –140 ), Figure 15. AD9683-170 Two-Tone FFT with f IN 0x09 = 0x21) –100 –120 –140 –32.5 –21.0 – ...
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... SFDR (dBc SNR (dBFS 100 110 120 130 140 150 160 170 SAMPLE RATE (MSPS) Figure 17. AD9683-170 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 90.1 MHz IN 700000 598772 600000 521038 500000 400000 384443 300000 200000 138113 100000 41248 ...
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... Figure 26. AD9683-250 Single-Tone SNR/SFDR vs. Input Frequency (f = 305.1 MHz IN –20 –40 –60 –80 –100 –120 –30 –20 –10 0 Figure 27. AD9683-250 Two-Tone SFDR/IMD3 vs. Input Amplitude ( –20 –40 –60 –80 –100 –120 Figure 28. AD9683-250 Two-Tone SFDR/IMD3 vs. Input Amplitude ( Rev Page 100 ...
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... Figure 30. AD9683-250 Two-Tone FFT with f = 184.12 MHz 187.12 MHz, f IN1 IN2 100 100 125 = 92.12 MHz, Figure 31. AD9683-250 Single-Tone SNR/SFDR vs. Sample Rate (f IN2 700000 600000 500000 400000 300000 200000 100000 100 125 = 250 MSPS S Rev Page SFDR (dBc) SNR (dBFS) ...
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... AD9683 EQUIVALENT CIRCUITS AVDD VIN Figure 33. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 34. Equivalent Clock lnput Circuit 0.5pF AVDD RFCLK 10kΩ BIAS CONTROL Figure 35. Equivalent RF Clock lnput Circuit DRVDD DRVDD 3mA 3mA R TERM SERDOUT0± ...
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... Application Note, Frequency Domain AN-827 Converters, ” for more BIAS PAR1 PAR2 PAR1 S PAR2 S BIAS Figure 43. Switched Capacitor Input AD9683 are not internally dc biased. CM ADA4930-1 AD9683 Application “Transformer 0.5 × AVDD (or AD9683 in a differential ...
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... FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9683. The full-scale input range can be adjusted by varying the reference voltage via the SPI. The input span of the ADC tracks the reference voltage changes linearly ...
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... AD9683 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9683, yet preserves the fast rise and fall times of the clock, which are critical to low jitter performance. CLOCK ...
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... Jitter Considerations section. Figure 54 shows the preferred method of clocking when using the RF clock input on the AD9683 recommended that a 50 Ω transmission line be used to route the clock signal to the RF clock input of the high frequency nature of the signal ...
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... Figure 57. AD9683-250 SNR vs. Input Frequency and Jitter Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9683. Separate the power supplies for the clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. ...
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... Figure 59 shows a simplified block diagram of the JESD204B link. The The converter data is output to SERDOUT0+/SERDOUT0−. By default, in the AD9683, the 14-bit converter word is divided into two octets (eight bits of data). Bit 0 (MSB) through Bit 7 are in the first octet, and the second octet contains Bit 8 through Bit 13 (LSB) and two tail bits ...
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... JESD204B allows parameters to identify the device and lane. These parameters are transmitted during the ILAS phase, and they are accessible in the internal registers. Rev Page AD9683 Bit 0 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) DID[7:0] BID[3:0] LID[4:0] L[4:0] F[7:0] K[4:0] M[7:0] N[4:0] N’[4:0] S[4:0] CF[4:0] Reserved, don’t care Reserved, don’t care FCHK[7:0] AD9683 ...
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... Verify read only values: lanes per link (L), octets per frame (F), number of converters (M), and samples per converter per frame (S). The AD9683 based on other settings, particularly the quick configuration register selection. The read only values here are available in the register map for verification. ...
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... Last octet in frame repeated from previous frame Last octet in frame repeated from previous frame Last octet in frame equals D28.7 Last octet in frame equals D28.3 Last octet in frame equals D28.7 Rev Page AD9683 ADC SERDOUT0± JESD204B TEST PATTERN 10-BIT SERIALIZER SERDOUT0± ...
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... To change the output data format to offset binary, see the CM CM Memory Map section (Address 0x14 in Table 17). Rev Page digital outputs can interface with custom ASICs and AD9683 (that is, the common-mode voltage is 0.9 V for a 100Ω DRVDD DIFFERENTIAL TRACE PAIR SERDOUT0+ 100Ω ...
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... Rev Page BER1: BATHTUB – –2 1 –4 1 –6 1 –8 1 –10 1 –12 1 –14 1 –16 1 –0.5 0 0.5 ULS T AT BER1: BATHTUB – –2 1 –4 1 –6 1 –8 1 –10 1 –12 1 –14 1 –16 1 –0.5 0 0.5 ULS includes circuitry that is useful in applications AD9683 3 – 3 – ...
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... AD9683 Fast Threshold Detection (FD) The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located in Address 0x47 and Address 0x48. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of seven clock cycles ...
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... Clearing this bit restarts dc correction and adds the currently calculated value to the data. DC CORRECTION ENABLE BITS Setting Bit 1 of Address 0x40 enables dc correction for use in the output data signal path. Rev Page AD9683 ...
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... The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9683. The SCLK pin and the CS pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. ...
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... Allows the user to set the reference voltage SCLK DON’T CARE R SDIO DON’T CARE t t HIGH CLK t LOW A12 A11 A10 Figure 67. Serial Port Interface Timing Diagram Rev Page DON’T CARE AD9683 DON’T CARE ...
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... Address 0x18). If the entire address location is open (for example, Address 0x13), do not write to this address location. Default Values After the AD9683 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). ...
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... Clock divider ratio relative to 0x00 the encode clock: 0x00 = divide by 1, 0x01 = divide by 2, 0x02 = divide by 3, … 0x07 = divide by 8 0x00 0x00 AD9683 Notes Read only DCS enabled if clock divider enabled Read only Clock divide values other than 0x00 automatically ...
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... AD9683 Reg Addr Reg Addr Bit 7 (Hex) Name (MSB) Bit 6 0x14 Output mode JESD204B CS bits assignment (in conjunction with Address 0x72): 000 = {overrange||underrange, valid}, 001 = {overrange, underrange}, 010 = {overrange||underrange, blank}, 011 = {blank, valid}, 100 = {blank, blank}, 101 = {underrange, overrange}, 110 = {valid, overange||underrange}, ...
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... Enable dc 0x00 correction 0x00 0x00 Enable fast 0x00 detect if output 0x00 Reserved; JESD204B 0x14 set to 1 link power- down; set high while configuring link parameters Invert Reserved; 0x00 transmit set to 0 bits 0x00 0111 = reserved, AD9683 Notes Always reads back 0x00 ...
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... AD9683 Reg Addr Reg Addr Bit 7 (Hex) Name (MSB) Bit 6 0x65 JESD204B BID config 0x67 JESD204B LID config 0x6E JESD204B JESD204B scrambler (SCR) scrambling and lane (L) (SCR configuration disabled enabled 0x6F JESD204B parameter, F 0x70 JESD204B parameter, K set value of K per JESD204B specifications, but must also be a multiple of four octets ...
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... Bits[5:2] of Address 0x40 (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9683 ADC sample rate in hertz. CLK Bit 1—Enable dc correction Setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...
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... AD9683 Bit 1—Reserved Bit 0—Enable fast detect output Setting this bit high enables the output of the upper threshold FD comparator to drive the FD output pin. Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Address 0x48, Bit 7—Reserved Address 0x48, Bits[6:0]—Fast detect upper threshold[14:8] Address 0x47, Bits[7:0]— ...
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... JESD204B Output Driver Control (Address 0x80) Bits[7:1]—Reserved Bit 1—JESD204B driver power-down When this bit is set low, the JESD204B output drivers are enabled. When this bit is set high, the JESD204B output drivers are powered down. Rev Page AD9683 ...
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... AD9683 JESD204B LMFC Offset (Address 0x8B) Bits[7:5]—Reserved Bits[4:0]—Local multiframe clock phase offset value These bits are the reset value for the local multiframe clock (LMFC) phase counter when SYSREF± is asserted. These bits are used in applications requiring deterministic delay. ...
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... Data Sheet APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD9683 recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9683 recommended that two separate 1 ...
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... SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9683BCPZ-170 −40°C to +85°C AD9683BCPZRL7-170 −40°C to +85°C AD9683-170EBZ −40°C to +85°C AD9683BCPZ-250 −40°C to +85°C AD9683BCPZRL7-250 −40°C to +85°C AD9683-250EBZ −40°C to +85° RoHS Compliant Part. 1 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...