AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 30

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

AD9683
Fast Threshold Detection (FD)
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located in Address 0x47 and Address 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
seven clock cycles. The approximate upper threshold magnitude
is defined by
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Address 0x49 and Address 0x4A. The fast
detect lower threshold register is a 16-bit register that is compared
with the signal magnitude at the output of the ADC. This
FD
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/2
13
)
Figure 66. Threshold Settings for FD Signals
LOWER THRESHOLD
TIMER RESET BY
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RISE ABOVE
DWELL TIME
comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
For example, to set an upper threshold of −6 dBFS, write
0x0FFF to those registers, and to set a lower threshold of
−10 dBFS, write 0x0A1D to those registers.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located in Address 0x4B and Address 0x4C.
The operation of the upper threshold and lower threshold registers,
along with the dwell time registers, is shown in Figure 66.
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/2
UPPER THRESHOLD
DWELL TIME
13
)
LOWER THRESHOLD
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
Data Sheet