AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 22

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

AD9683
RF Clock Input Options
The
between 625 MHz to 1.5 GHz. The equivalent RF clock input
circuit is shown in Figure 53. The input is self biased to 0.9 V and is
typically ac-coupled. The input has a typical input impedance of
10 kΩ in parallel with 0.5 pF at the RFCLK pin.
It is recommended that the RF clock input of the
driven with a PECL or sine wave signal with a minimum signal
amplitude of 600 mV p-p. Regardless of the type of signal being
used, clock source jitter is of the most concern, as described in the
Jitter Considerations section. Figure 54 shows the preferred method
of clocking when using the RF clock input on the AD9683. It is
recommended that a 50 Ω transmission line be used to route
the clock signal to the RF clock input of the
high frequency nature of the signal; terminate the transmission
line close to the RF clock input.
Figure 56 shows the RF clock input of the
from the LVPECL outputs of the AD9515. The differential LVPECL
output signal from the
signal using an RF balun or RF transformer. The RF balun
configuration is recommended for clock frequencies associated
with the RF clock input.
Input Clock Divider
The
divide the Nyquist input clock by integer values between 1 and 8.
The RF clock input uses an on-chip predivider to divide the clock
input by four before it reaches the 1 to 8 divider. This allows
higher input frequencies to be achieved on the RF clock input. The
AD9683
AD9683
RFCLK
RF CLOCK
RF clock input supports a single-ended clock
contains an input clock divider with the ability to
INPUT
Figure 53. Equivalent RF Clock Input Circuit
CONTROL
Figure 54. Typical RF Clock Input Circuit
BIAS
0.5pF
10kΩ
50Ω Tx LINE
AD9515
is converted to a single-ended
50Ω
0.1µF
RFCLK
INTERNAL
CLOCK DRIVER
AD9683
ADC
AD9683
AD9683
being driven
due to the
be
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divide ratios can be selected using Address 0x09 and Address 0x0B.
Address 0x09 is used to set the RF clock input, and Address 0x0B
can be used to set the divide ratio of the 1 to 8 divider for both
the RF clock input and the Nyquist clock input. For divide ratios
other than 1, the duty cycle stabilizer (DCS) is automatically
enabled.
The
SYSREF input. Bit 1 and Bit 2 of Address 0x3A allow the clock
divider to be resynchronized on every SYSREF signal or only on
the first signal after the register is written. A valid SYSREF causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned to
guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The
edge, providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock input
duty cycles without affecting the performance of the AD9683.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the DCS. The duty cycle control
loop does not function for clock rates of less than 40 MHz
nominally. The loop has a time constant associated with it that
must be considered when the clock rate can change dynamically.
A wait time of 1.5 µs to 5 µs is required after a dynamic clock
frequency increase or decrease before the DCS loop is relocked
to the input signal. During the time that the loop is not locked,
the DCS loop is bypassed, and the internal device timing is
dependent on the duty cycle of the input clock signal. In such
applications, it may be appropriate to disable the DCS. In all
other applications, enabling the DCS circuit is recommended
to maximize ac performance.
AD9683
AD9683
NYQUIST
CLOCK
RFCLK
contains a DCS that retimes the nonsampling (falling)
clock divider can be synchronized using the external
Figure 55. Clock Divider Circuit
÷2 OR ÷4
÷1 TO ÷8
DIVIDER
Data Sheet