AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 39

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

Data Sheet
Bit 4—JESD204B standby mode
This bit controls the state of the JESD204B digital circuitry when
the external PDWN pin is used to place the device into standby.
If this bit is 0, the JES204B digital circuitry is not placed into
standby. When this bit is 1, the JESD204B circuitry is placed
into standby when the PDWN pin is asserted and Bit 5 is 1.
Bits[3:2]—JESD204B power modes
These bits control the power modes of the JESD204B digital
circuitry. When Bits[3:2] = 00, the JESD204B digital circuitry
is in normal mode. When Bits[3:2] = 01, the JESD204B digital
circuitry is in power-down mode with the PLL off, serializer off,
clocks stopped, and the digital circuitry held in reset. When
Bits[3:2] = 10 the JESD204B digital circuitry is placed into standby
mode with the PLL on, serializer off, clocks stopped, and the
digital circuitry held in reset.
Bits[1:0]—ADC power modes
These bits select power mode for the ADC excluding the
JESD204B digital circuitry. When Bits[1:0] = 00, the ADC is in
normal mode. When Bits[1:0] = 01, the ADC is placed into
power-down mode, and when Bits[1:0] = 10, the ADC is placed
into standby mode.
Output Mode (Address 0x14)
Bits[7:5]—JESD204B CS Bits Assignment
These bits control the function of the CS bits in the JESD204B
serial data stream.
Bit 4—ADC output disable
If this bit is set, the output data from the ADC is disabled.
Bit 3—Open
Bit 2—ADC data invert
If this bit is set, the output data from the ADC is inverted.
Bits[1:0]—Data Format Select
These bits select the output data format. When Bits[1:0] = 00,
the output data is in offset binary format, and when Bits[1:0] = 01,
the output data is in twos complement format.
SYNCINB±/SYSREF± Control (Address 0x3A)
Bits[7:5]—Reserved
Bit 4—JESD204B realign SYNCINB±
When this bit is set low, the JESD204B link operates in normal
mode. When this bit is high, the JESD204B link realigns on
every active SYNCINB± assertion.
Bit 3—JESD204B realign SYSREF±
When this bit is set low, the JESD204B link operates in normal
mode. When this bit is high, the JESD204B link realigns on
every active SYSREF± assertion.
Bit 2—SYSREF± mode
When this bit is set low, the clock dividers are continuously
reset on each SYSREF± assertion. When this bit is high, the
clock dividers are reset on the next rising edge of SYSREF± only.
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Bit 1—SYSREF± enable
When this bit is set low, the SYSREF± input is disabled. When
this bit is high, the SYSREF± input is enabled.
Bit 0—Enable SYNCINB± buffer
When this bit is set low, the SYNCINB± input buffer is disabled.
When this bit is high, the SYNCINB± input buffer is enabled.
DC Correction Control (Address 0x40)
Bit 7—Reserved
Bit 6—Freeze dc correction
When Bit 6 is set low, the dc correction is continuously calculated.
When Bit 6 is set high, the dc correction is no longer updated to
the signal monitor block, which holds the last dc value calculated.
Bits[5:2]—DC correction bandwidth select
Bits[5:2] set the averaging time of the signal monitor dc correction
function. This 4-bit word sets the bandwidth of the correction
block, according to the following equation:
where:
k is the 4-bit value programmed in Bits[5:2] of Address 0x40
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
f
Bit 1—Enable dc correction
Setting this bit high causes the output of the dc measurement
block to be summed with the data in the signal path to remove
the dc offset from the signal path.
Bit 0—Reserved
DC Correction Value 0 (Address 0x41)
Bits[7:0]—DC correction value LSB[7:0]
These bits are the LSBs of the dc correction value.
DC Correction Value 1 (Address 0x42)
Bits[7:0]—DC correction value MSB[15:8]
These bits are the MSBs of the dc correction value.
Fast Detect Control (Address 0x45)
Bits[7:5]—Reserved
Bit 4—FD pin function
When this bit is set low, the FD pin functions as the fast detect
output. When this pin is set high, the FD pin functions as the
overrange indicator.
Bit 3—Force FD output enable
Setting this bit high forces the FD output pin to the value written to
Bit 2 of this register (Address 0x45). This enables the user to
force a known value on the FD pin for debugging.
Bit 2—Forced FD Output Value
The value written to Bit 2 is forced on the FD output pin when
Bit 3 is written high.
CLK
is the AD9683 ADC sample rate in hertz.
DC
_
Corr
_
BW
=
2
−
k
−
14
×
2
f
CLK
×
π
AD9683