AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

AD9683
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the JESD204B
specification. The 14-bit word requires two octets to transmit all
the data. The two octets (MSB and LSB), where F = 2, make up
a frame. During normal operating conditions, frame alignment
is monitored via alignment characters, which are inserted under
certain conditions at the end of a frame. Table 14 summarizes the
conditions for character insertion along with the expected characters
under the various operation modes. If lane synchronization is
enabled, the replacement character value depends on whether
the octet is at the end of a frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
Digital Outputs and Timing
The
default. The driver current is derived on chip and sets the output
current at each output equal to a nominal 3 mA. Each output
presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 600 mV p-p swing at the receiver
(see Figure 62). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the
termination voltage must be DRVDD/2; otherwise, ac coupling
capacitors can be used to terminate to any single-ended voltage.
OUTPUT SWING = 600mV p-p
AD9683
SERDOUT0+
SERDOUT0–
DRVDD
Figure 62. AC-Coupled Digital Output Termination Example
has differential digital outputs that power up by
0.1µF
0.1µF
DIFFERENTIAL
TRACE PAIR
100Ω
100Ω
V
OR
RXCM
V
CM
RECEIVER
= Rx V
CM
Rev. 0 | Page 28 of 44
The
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible. The common mode
of the digital output automatically biases itself to half the supply
of the
supply of 1.8 V) if a dc-coupled connection is used (see Figure 63).
For a receiver logic that is not within the bounds of the DRVDD
supply, use an ac-coupled connection. Simply place a 0.1 µF
capacitor on each output pin and derive a 100 Ω differential
termination close to the receiver side.
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 64 shows an example of the digital output (default) data eye
and time interval error (TIE) jitter histogram and bathtub curve for
the
Additional SPI options allow the user to further increase the output
driver voltage swing or enable preemphasis to drive longer trace
lengths (see Address 0x15 in Table 17). The power dissipation
of the DRVDD supply increases when this option is used. See the
Memory Map section for more details.
The format of the output data is twos complement by default.
To change the output data format to offset binary, see the
Memory Map section (Address 0x14 in Table 17).
AD9683
OUTPUT SWING = 600mV p-p
AD9683
AD9683
SERDOUT0+
SERDOUT0–
Figure 63. DC-Coupled Digital Output Termination Example
DRVDD
lane running at 5 Gbps.
digital outputs can interface with custom ASICs and
(that is, the common-mode voltage is 0.9 V for a
DIFFERENTIAL
TRACE PAIR
100Ω
100Ω
RECEIVER
V
CM
Data Sheet
= DRVDD/2