PC48F4400P0TB0EE NUMONYX, PC48F4400P0TB0EE Datasheet - Page 18

• Manufacturer Part Number: PC48F4400P0TB0EE
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6:
6.2
Datasheet
18
Configuration
blank check
Protection
Suspend
Mode
other
Command Codes and Definitions (Sheet 2 of 2)
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 7, “Command Bus Cycles” on page
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
Code
0xD0
0xD0
0xBC
0xD0
0xB0
0x60
0x01
0x2F
0xC0
0x60
0x03
0xEB
Program or Erase
Suspend
Suspend Resume
Block lock Setup
Block lock
Unlock Block
Lock-Down Block
Protection program
setup
Read Configuration
Register Setup
Read Configuration
Register
Blank Check
Blank Check
Confirm
Extended Function
Interface command
Device Mode
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR.2 (program
suspended) or SR 6 (erase suspended), along with SR.7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
This command issued to any device address resumes the suspended program
or block-erase operation.
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets SR.5 and SR.4,
indicating a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
First cycle of a 2-cycle command; prepares the device for a OTP register or
Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm to program data the
the OTP array.
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR.5 and SR.4,
indicating a command sequence error.
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[15:0]to the Read Configuration
Register. Following a Configure RCR command, subsequent read operations
access array data.
First cycle of a 2-cycle command; initiates the Blank Check operation on a
main block.
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the main array block.
This command is used in extended function interface. first cycle of a multiple-
cycle command second cycle is a Sub-Op-Code, the data written on third
cycle is one less than the word count; the allowable value on this cycle are 0
through 511. The subsequent cycles load data words into the program buffer
at a specified address until word count is achieved.
19. Several commands are used to modify
Description
Order Number: 320003-09
P33-65nm
Mar 2010