PC48F4400P0TB0EE NUMONYX, PC48F4400P0TB0EE Datasheet - Page 31

• Manufacturer Part Number: PC48F4400P0TB0EE
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P33-65nm
10.1.4
Figure 8:
Note:
10.1.5
Note:
Datasheet
31
LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
Block Locking State Diagram
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 7.3, “Read Device Identifier” on page
addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the
addressed block’s lock-down bit.
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR.7 and SR.6 are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR.4 and SR.5. If a command sequence error occurs during an erase
suspend, SR.4 and SR.5 remains set, even after the erase operation is resumed. Unless
the Status Register is cleared using the Clear Status Register command before
resuming the erase operation, possible erase errors may be masked by the command
sequence error.
W P # = V
W P # = V
IL
I H
= 0
= 1
P G M /E R A S E
A L L O W E D
[ 0 0 0 ]
[ 1 1 0 ]
[ 1 0 0 ]
V i r t u a l l o c k -
D 0 h
D 0 h
L K /
L K /
D 0 h
d o w n
L K /
0 1 h o r 2 F h
2 F h
L K /
L K /
0 1 h
L K /
0 1 h
L K /
[ 0 1 0 ]
c o m m a n d s
22). Data bits DQ[1:0] display the
A n y L o c k
P R E V E N T E D
P G M /E R A S E
2 F h
L K /
[ 0 0 1 ]
[ 0 1 1 ]
[ 1 1 1 ]
[ 1 0 1 ]
W P # t o g g l e
2 F h
L K /
i s d i s a b l e d b y
L o c k e d - d o w n
L o c k e d - d o w n
W P # = V
R e s e t D e f a u l t
R e s e t D e f a u l t
P o w e r - U p /
Order Number:320003-09
P o w e r - U p /
I H
Mar 2010