PC48F4400P0TB0EE NUMONYX, PC48F4400P0TB0EE Datasheet - Page 28

• Manufacturer Part Number: PC48F4400P0TB0EE
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.0
9.1
9.2
Datasheet
28
Erase Operation
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the
address of the block to be erased (see
page
block to be erased. If the device is placed in standby (CE# deasserted) during an erase
operation, the device completes the erase operation before entering standby. VPP must
be above V
on page
During a block erase, the WSM executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros
only by programming the block.
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR.0 indicates whether the addressed block is erasing. Status
Register bit SR.7 is set upon erase completion.
Status Register bit SR.7 indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR.5 indicates an erase
failure if set. SR.3 set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR.1 set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
Blank Check
The Blank Check operation determines whether a specified main block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. so Blank Check can be used to determine whether
or not a prior erase operation was successful; this includes erase operations that may
have been interrupted by power loss.
Blank check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Blank Check Setup command to the
block address. Next, the Check Confirm command is issued along with the same block
address. When a successful command sequence is entered, the device automatically
enters the Read Status State. The WSM then reads the entire specified block, and
determines whether any bit in the block is programmed or over-erased.
18). Next, the Block Erase Confirm command is written to the address of the
76).
PPLK
and the block must be unlocked (see
Section 6.2, “Device Command Bus Cycles” on
Figure 35, “Block Erase Flowchart”
Order Number: 320003-09
P33-65nm
Mar 2010