PC48F4400P0TB0EE NUMONYX, PC48F4400P0TB0EE Datasheet - Page 35

• Manufacturer Part Number: PC48F4400P0TB0EE
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P33-65nm
Table 11: Read Configuration Register Description (Sheet 2 of 2)
11.1.1
11.1.2
Datasheet
35
3
2:0
Burst Wrap (BW)
Burst Length (BL[2:0])
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 MHz, and there will be zero WAIT States when
bursting within the word line. Please also refer to
(EOWL) Considerations” on page 37
Refer to
Table 12, “LC and Frequency Support” on page 36
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Figure 9
shows the data output latency for the different
for more information on EOWL.
Section 11.1.3, “End of Word Line
for Latency Code Settings.
Order Number:320003-09
Mar 2010