PC48F4400P0TB0EE NUMONYX, PC48F4400P0TB0EE Datasheet - Page 87

• Manufacturer Part Number: PC48F4400P0TB0EE
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P33-65nm
Appendix C Revision History
Datasheet
87
June 2008
Aug 2009
Dec 2008
Nov 2008
Sep 2008
July 2008
May 2008
Mar 2010
Apr 2009
Date
Revision
09
08
07
06
05
04
03
02
01
Description
Program performance update in front page,
Specifications”
t
Erase/program suspend latency specification update,
Specifications” on page 58
Leaded TSOP part EOL.
Burst latency update and 40MHz spec update,
on page 36
Clarify the capacitance,
Ordering Information update.
Update the Block lock Operations, Program Suspend/Resume, Erase Suspend/Resume flowcharts in
Figure 36
Align the sequence error description in
Add TSOP 40Mhz Burst Spec, f
on page 49
Add note 7 in buffer program flowchart
Update V
Update CFI 0x2A data in
Add 512 Mbit (256/256) memory map in
page 7
Correct RCR.4, RCR.5, RCR.7 and RCR.9 definitions in
Register Description” on page 34
Correct A
Query Structure Output of x16 Devices” on page 62
Correct Page buffer address bits to Four on
Read” on page 21
Correct VHH to V
Update the Buffer program flowchart to reflect the read status register;
minor wording modification;
Return to StrataFlash;
Update the buffer program comments for cross 512-Word boundary;
Remove 128M related contents from this document;
Correct A24 to A25 for virtual CE description in section 1.3;
Remove Numonyx Confidential;
Updated Axcell
Remove 64M related content;
Added W28 AC specification;
Fixed Buffered Program Command error in figure 38;
Updated block locking state diagram;
Updated Address range in Memory Map figure;
Changed LSB Address from A0 to A1 in figure7 under dual die configurations section;
Changed LSB Address in ballout and pinout description from A0 back to A1 to match P33 130nm.
Corrected SCSP order information
Initial release
DVWH
specification comments,
IL
0
to A
undershoot and overshoot of Note 2 in
,
Figure 37
.
.
TM
1
signal naming and remove invalid x8 information in
PPH
trademark;
and CFI.
on
.
Table 19, “DC Current Characteristics” on page 46
Table 22, “Capacitance” on page 49
Section A.1, “Common Flash Interface”
,
Figure 37
CLK
Table 24, “AC Write Specifications” on page 54
, t
.
CLK
, t
, backward compatible with 130nm.
Table 11
Figure 33
CHQV
Figure 1, “P33-65nm Memory Map” on
Section 7.1, “Asynchronous Page-Mode
Section 25, “Program and Erase
, t
Table 12, “LC and Frequency Support”
CHTV
.
Table 20
,
.
Table 23, “AC Read Specifications -”
Table 25, “Program and Erase
Table 11, “Read Configuration
.
Table 29, “Example of
.
Order Number:320003-09
.
note.
Mar 2010
.