PC48F4400P0TB0EE NUMONYX, PC48F4400P0TB0EE Datasheet - Page 25

• Manufacturer Part Number: PC48F4400P0TB0EE
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P33-65nm
8.3.1
8.3.2
Note:
8.3.3
Datasheet
25
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
BEFP Requirements and Considerations
BEFP requirements:
BEFP considerations:
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4
is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR.0 indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 512 words. During the buffer-loading sequence, data is
• Case temperature: T
• Nominal VCC
• VPP driven to V
• Target block must be unlocked before issuing the BEFP Setup and Confirm
• The first-word address for the block to be programmed must be held constant from
• The first-word address must align with the start of an array buffer boundary. Word
• For optimum performance, cycling must be limited below 50 erase cycles per block.
• BEFP programs one block at a time; all buffer data must fall within a single block. If
• BEFP cannot be suspended
• Programming to the flash memory array can occur only when the buffer is full. If
commands
the setup phase through all data streaming into the target block, until transition to
the exit phase is desired.
buffer boundaries in the array are determined by A[8:0] (0x000 through 01FF); the
alignment start point is A[8:0] = 0x000.
Some degradation in performance may occur is this limit is exceeded, but the
internal algorithm continues to work properly.
the internal address counter increments beyond the block’s maximum address,
addressing wraps around to the beginning of the block.
the number of words is less than 512, remaining locations must be filled with
0xFFFF.
PPH
C
= 30 °C ± 10 °C
Order Number:320003-09
Mar 2010