TE28F640J3C115SL7HA Intel, TE28F640J3C115SL7HA Datasheet - Page 16

• Manufacturer Part Number: TE28F640J3C115SL7HA
• Description: IC FLASH 64MBIT 115NS 56TSOP
• Manufacturer: Intel

Specifications of TE28F640J3C115SL7HA

• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 860794

256-Mbit J3 (x8/x16)
4.4
16
A[MAX:1]
Symbol
D[15:8]
BYTE#
VCCQ
D[7:0]
VPEN
Table 3.
CE0,
CE1,
WE#
VCC
CE2
RP#
OE#
STS
A0
Input/Output
Input/Output
Open Drain
Signal Descriptions
Table 3
Signal Descriptions (Sheet 1 of 2)
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
describes active signals used.
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer
is turned off when BYTE# is high).
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle.
32-Mbit: A[21:0]
64-Mbit: A[22:0]
128-Mbit: A[23:0]
256-Mbit: A[24:0]
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs
commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read
mode. Data is internally latched during write operations.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see
levels.
All timing specifications are the same for these three signals. Device selection occurs with the
first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first
edge of CE0, CE1, or CE2 that disables the device (see
RESET/ POWER-DOWN: RP#-low resets internal automation and puts the device in power-
down mode. RP#-high enables normal operation. Exit from reset sets the device to read array
mode. When driven low, RP# inhibits write operations which provides data protection during
power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active
low. Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the STATUS signal,
see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0],
while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-
high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the
lowest-order address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With V
CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when V
I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to V
PEN
CC
≤ V
≤ V
PENLK
LKO
. Device operation at invalid Vcc voltages should not be attempted.
, memory contents cannot be altered.
Name and Function
Table 13 on page
Table 13 on page
33), power reduces to standby
33).
CC
.
Datasheet