MD2534-D2G-X-P SanDisk, MD2534-D2G-X-P Datasheet - Page 62

• Manufacturer Part Number: MD2534-D2G-X-P
• Description: IC MDOC H3 2GB FBGA
• Manufacturer: SanDisk

Specifications of MD2534-D2G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Note: In Burst write the wait states start from the N
The LATENCY field controls the number of clock cycles between mDOC H3 sampling CE#
being asserted and when the first word of data is available to be latched by the host. This number
of clock cycles is equal to 2 + LATENCY.
Note: If HOLD = 1, then the data is available to be latched on this clock and on the subsequent
clock.
The CLK input can be toggled continuously or can be halted. When halting the CLK input, the
following guidelines must be observed:
Burst should be disabled before accessing mDOC H3 registers or IPL. This can be done by
writing to the BURST_EN bit in Burst Mode Control Registers, which is the only accessible
register in burst mode.
Notes: 1. Burst mode has to be turned off in order to respond to the mDOC H3 interrupt
9.9
When connecting mDOC H3 using a standard interface, up to two devices can be cascaded with
no external decoding circuitry. Figure 13 illustrates the configuration required to cascade two
devices on the host bus (only the relevant cascading signals are included in this figure, although
all other signals must also be connected). All balls of the cascaded devices must be wired in
common, except for ID0. The ID ball values determine the identity of each device – the first
device is identified by connecting the ID ball as 0, and the second device by connecting the ID
ball as 1. Systems that use only one mDOC H3 should connect ID0 to GND.
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• After asserting OE# and CE#, LATENCY + 2 CLK cycles are required prior to
• If the HOLD bit is set to 0, the host must provide one rising CLK edge for each word
• If the HOLD bit is set to 1, the host must provide two rising CLK edges for each word
• Subsequent toggling of the CLK is optional.
2. Burst mode can be used only in conjunction with DMA operation, since the status
3. Burst Write mode can be aborted by writing to Burst Write Mode Exit register.
Device Cascading
latching the first word
read, except for the last word latched, for which CLK does not need to be toggled.
read, except for the last word, for which the second of the two CLK rising edges is not
required.
requests (generated during combined Burst and DMA operation).
register cannot be polled in the middle of a burst transfer, to determine command
completion.
Data Sheet (Preliminary) Rev. 0.2
th
word.
mDOC H3 Embedded Flash Drive
92-DS-1205-10