MD2534-D2G-X-P SanDisk, MD2534-D2G-X-P Datasheet - Page 63

• Manufacturer Part Number: MD2534-D2G-X-P
• Description: IC MDOC H3 2GB FBGA
• Manufacturer: SanDisk

Specifications of MD2534-D2G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

9.10 Platform-Specific Issues
This section discusses hardware design issues for major embedded RISC processor families.
9.10.1 Wait State
Wait states can be implemented only when mDOC H3 is designed in a bus that supports a Wait
state insertion, and supplies a WAIT signal.
9.10.2 Big and Little Endian Systems
mDOC H3 is a Little Endian device. Therefore, byte lane 0 (D[7:0]) is its Least Significant Byte
(LSB) and byte lane 1 (D[15:8]) is its Most Significant Byte (MSB). Within the byte lanes, bit D0
and bit D8 are the least significant bits of their respective byte lanes. mDOC H3 can be connected
to a Big Endian device in one of two ways:
1.
2. If needed, set the SWAP bits in the Endian Control register. This enables byte swapping
9.10.3 Busy Signal
The Busy signal (BUSY#) indicates that mDOC H3 has not yet completed internal initialization.
After reset, BUSY# is asserted while the IPL is downloaded into the internal boot block. Once the
download process is completed, BUSY# is de-asserted. It can be used to delay the first access to
mDOC H3 until it is ready to accept valid cycles.
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Make sure to identify byte lane 0 and byte lane 1 of your processor. Then, connect the data
bus so that the byte lanes of the CPU match the byte lanes of mDOC H3. Pay special
attention to processors that also change the bit ordering within the bytes (for example,
PowerPC). Failing to follow these rules results in improper connection of mDOC H3, and
prevents the DOC driver from identifying it.
when used with big endian 16-bit hosts. Please note the Endian Control register cannot be set
while A0 is pulled high.
WE#
OE#
CE#
Figure 13: Standard Interface, Cascaded Configuration
V SS
Data Sheet (Preliminary) Rev. 0.2
ID0
CE#
OE#
WE#
1st
VCCQ
ID0
CE#
OE#
WE#
2nd
mDOC H3 Embedded Flash Drive
92-DS-1205-10