ISL9206ADRTZ-T Intersil, ISL9206ADRTZ-T Datasheet

IC AUTHENTICATION DEVICE 8-TDFN

ISL9206ADRTZ-T

Manufacturer Part Number
ISL9206ADRTZ-T
Description
IC AUTHENTICATION DEVICE 8-TDFN
Manufacturer
Intersil
Series
FlexiHash+™r
Datasheet

Specifications of ISL9206ADRTZ-T

Function
Battery Authentication
Battery Type
Li-Ion, Li-Pol, NiMH
Voltage - Supply
2.6 V ~ 4.8 V
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Pinouts
FlexiHash+™ For Battery Authentication
The ISL9206A is a highly cost-effective fixed-secret hash
engine based on Intersil’s second generation FlexiHash™
technology. The device authentication is achieved through a
challenge-response scheme customized for low-cost
applications, where cloning via eavesdropping without
knowledge of the device’s secret code is not economically
viable. When used for its intended applications, the
ISL9206A offers the same level of effectiveness as other
significantly more expensive high-maintenance hash
algorithm and authentication schemes.
The ISL9206A has a wide operating voltage range, and is
suitable for direct powering from a 1-cell Li-ion/Li-Poly or a
3-cell series NiMH battery pack. The ISL9206A can also be
powered by the XSD bus when the bus pull-up voltage is
3.3V or higher. The device connects directly to the cell
terminals of a battery pack, and includes on-chip voltage
regulation circuit, POR, and a non-crystal based oscillator for
bus timing reference.
Communication with the host is achieved through a single
wire XSD interface (a light-weight subset of Intersil’s ISD bus
interface). The XSD bus is compatible for use with serial ports
offered by all 8250 compatible UART’s or a single GPIO
(General Purpose Input and Output) pin of a microprocessor.
A clone prevention solution utilizing the ISL9206A offers
safety and revenue protection at the lowest cost and power,
and is suitable for protection against after-market
replacement for a wide variety of low-cost applications.
Ordering Information
ISL9206ADHZ-T*
ISL9206ADRTZ-T* 06A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
VDD
VSS
PART NUMBER
NC
NC
(Note)
1
2
3
4
(8 LD 2X3 TDFN)
TOP VIEW
ISL9206A
206A
MARKING
PART
8
7
6
5
XSD
NC
NC
TIO
®
RANGE (°C)
1
-25 to +85
-25 to +85
TEMP.
VDD
VSS
NC
Data Sheet
1
2
3
(5 LD SOT-23)
TOP VIEW
ISL9206A
5 Ld SOT-23
8 Ld 2x3 TDFN L8.2x3A
FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
PACKAGE
(Pb-free)
5
4
1-888-INTERSIL or1-888-468-3774
XSD
TIO
P5.064
DWG. #
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
PKG.
Features
• Challenge-response based authentication scheme using
• Fast and flexible authentication process. Multi-pass
• 16x8 OTP ROM stores up to three sets of 32-Bit
• FlexiHash+™ engine uses two sets of 32-Bit secrets for
• Non-unique mapping of the secret key to an 8-Bit
• Supports 1-cell Li-ion/Li-Poly and 3-cell series NiMH
• XSD single-wire host bus interface communicates with all
• True “Zero Power” Sleep mode (automatically entered
• 5 Ld SOT-23 or 8 Ld TDFN (2mmx3mm) packages
• -25°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
Applications
• Battery Pack Authentication
• Printer Cartridges
• Add-on Accessories
• Other Non-Monetary Authentication Applications
Related Literature
• Application Note AN1165 “ISL6296 Evaluation Kit”
• Application Note AN1167 “Implementing XSD Host Using
• Technical Brief TB363 “Guidelines for Handling and
32-Bit challenge code and 8-Bit authentication code.
authentication can be used to achieve the highest security
level if necessary.
host-selectable secrets with additional programmable
memory for storage of up to 48-Bits of ID code and/or pack
information.
authentication code generation.
authentication code maximizes hacking difficulty due to
need for exhaustive key search (superior to SHA-1).
battery packs (2.6V ~ 4.8V operation), or powered by the
XSD bus.
8250-compatible UART’s or a single GPIO. Supports CRC
on read data and transfer bit-rate up to 23kbps.
after a bus inactivity time-out period)
a GPIO”
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
July 30, 2008
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008. All Rights Reserved.
ISL9206A
FN6651.1

Related parts for ISL9206ADRTZ-T

ISL9206ADRTZ-T Summary of contents

Page 1

... MARKING RANGE (°C) ISL9206ADHZ-T* 206A -25 to +85 ISL9206ADRTZ-T* 06A -25 to +85 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

Page 2

... Thermal Resistance (Typical) + 0.5V SOT-23 Package (Note 2x3 TDFN Package (Notes Maximum Junction Temperature (Plastic Package +125°C Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -25°C to +85° SYMBOL TEST CONDITIONS V During normal operation DD ...

Page 3

Electrical Specifications Unless otherwise noted, all parameters are established over the operational supply voltage and temperature range of the device as follows: T limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not ...

Page 4

Typical Applications PACK+ XSD PACK- FIGURE 1. TYPICAL APPLICATION WITH THE ISL9206A POWERED BY THE BATTERY PACK+ XSD PACK- FIGURE 2. TYPICAL APPLICATION WITH THE ISL9206A POWERED BY THE XSD BUS Block Diagram VDD XSD VSS 4 ISL9206A R 2 ...

Page 5

Theory of Operation The ISL9206A contains all circuitry required to support battery pack authentication based on a challenge-response scheme. It provides a 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space for the storage 96-Bit of secret for the ...

Page 6

ASLP bit in DCFG) during OTP ROM programming. OTP ROM The 16-Byte OTP ROM memory is based on EEPROM technology and is incorporated into the ISL9206A for storage of ...

Page 7

The flow chart in Figure 6 summarizes the process that the host needs to execute. 32-BIT PSEUDO-RANDOM CHALLENGE WORD FROM HOST 64-BIT SECRET 32-BIT HASH FUNCTION FLEXIHASH+™ ENGINE 64-BIT HASH SEED 8-BIT AUTHENTICATION CODE FIGURE 5. AUTHENTICATION PROCESS ...

Page 8

... XSD Host Bus Interface Communication with the host is achieved through XSD, a light-weight subset of Intersil’s ISD single-wire bus interface. XSD is a programmable-rate pseudo-synchronous bidirectional host-initiated instruction-based serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication ...

Page 9

HOST OPEN-DRAIN Open-Drain PORT PIN Port Pin TX RX FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS XSD TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER SYMBOL Bit Time 0. ...

Page 10

OPCODE DESCRIPTION 00 Write Operation 01 Read Operation (normal) 10 Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the last read frame. 11 Sleep Mode Activation Access Instruction Frame The XSD access instruction ...

Page 11

TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL SYMBOL DESCRIPTION IFG Host inter-frame gap H IFG Device inter-frame gap D TA Host turn-around time H TA Device turn-around time D Passive CRC Support The CRC feature only supports the read ...

Page 12

... These registers are used during the battery pack authentication process. Table 10 describes the mapping of the Authentication registers. Bank 3 is reserved for Intersil production testing only and will not be accessible during normal operation. Accessing the Test and Trim Registers when not in test mode will result in a bus error ...

Page 13

ADDRESS NAME DESCRIPTION 2-00 SESL Secrets Selection 2-01 CHLG Challenge Code Register 2-05 AUTH Authentication Code Register TABLE 11. DEFAULT CONFIGURATION (DCFG) REGISTER SETTINGS BIT NAME TYPE DEFAULT 7:6 DAB[1: 5:4 SPD[1: eINT RW 1 ...

Page 14

ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET SET #3 (SE3A/B/C/D) These address locations store the optional third set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[0] bit at OTP ROM ...

Page 15

... One way is to use a spare UART (Universal Asynchronous Receiver/Transmitter). A GPIO (General Purpose Input/Output) can be used if no UART is available for the XSD communication. Refer to application note AN1167 available from Intersil for more information regarding how to implement the XSD bus within a microprocessor. Pull-up Resistor Selection ...

Page 16

Small Outline Transistor Plastic Packages (SOT23- 0.20 (0.008 0.10 (0.004 WITH PLATING b1 c BASE METAL ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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