ISL9206ADRTZ-T Intersil, ISL9206ADRTZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL9206ADRTZ-T
• Description: IC AUTHENTICATION DEVICE 8-TDFN
• Manufacturer: Intersil
• Series: FlexiHash+™r

Specifications of ISL9206ADRTZ-T

• Function: Battery Authentication
• Battery Type: Li-Ion, Li-Pol, NiMH
• Voltage - Supply: 2.6 V ~ 4.8 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

itself down. The flow chart in Figure 6 summarizes the
process that the host needs to execute.
It is recommended that device authentication be done once
in a while to maximize its effectiveness. Before a new
challenge code can be accepted by the device, the SESL
register must be re-written again to ensure that the original
seeds are re-loaded from the OTP ROM into the hash
engine prior to performing the next authentication code
calculation. Failure to follow the sequence will result is a bus
error, causing the sBER flag to be set in the STAT register.
SET-UP FOR DEVICE AUTHENTICATION SUPPORT
To configure the host and the ISL9206A to support device
authentication function, the pack manufacturer will need to
select at least 2 sets of 32-Bit secret codes. For greater
security, a third set of 32-Bit secret may be used. The
FlexiHash+™ engine requires two sets of 32-Bit secrets for
use in its hash calculation: the first set to define its the hash
function, and the second set to initialize its seed for the hash
calculation. These two sets can be selected from the same
secret location. The chosen secret codes are to be kept by
the pack manufacturer and maintained at utmost
confidentiality.
After the secrets have been determined, they are written into
the device’s OTP ROM. After verifying that the codes have
been written correctly, the relevant secrets’ lock-out bits at
the ROM address location 0-00 should be set. Once set, the
lock-out bits can no longer be cleared. Thereafter, read/write
access to the secret information will no longer be possible,
and the secret codes are made available only to the
FlexiHash+™ engine for generation of authentication code
based on a challenge code input from the host.
On the host side, the same secret codes will need to be kept,
and the same FlexiHash+™ engine will have to be
implemented in firmware. It is important that the secret
codes be stored scrambled in the host’s non-volatile memory
so that the secret information cannot be easily revealed by
monitoring signal transfer on the host PCB.
FIGURE 5. AUTHENTICATION PROCESS FLOW DIAGRAM
32-BIT HASH FUNCTION
64-BIT HASH SEED
64-BIT SECRET
FLEXIHASH+™
7
ENGINE
8-BIT AUTHENTICATION CODE
CHALLENGE WORD FROM HOST
32-BIT PSEUDO-RANDOM
ISL9206A
THE HASH ENGINE
The hash engine consists of a cascade of programmable
highly non-linear proprietary encoders. Details on the
proprietary encoder implementation will be made available to
users under NDA only.
FIGURE 6. FLOW CHART FOR AUTHENTICATION PROCESS
SELECT HASH FUNCTION AND SEED
CHALLENGE TO CHLG REGISTER
BY WRITING TO SESL REGISTER
RESULT FROM AUTH REGISTER,
BASED ON THE SAME SECRETS
READ THE AUTHENTICATION
WAKE UP ISL9206A USING A
CALCULATE THE EXPECTED
THE TWO RESULTS MATCH?
AFTER WAITING FOR 1 BT
AUTHENTICATION RESULT
REGULAR BREAK SIGNAL
SEND A 32-BIT RANDOM
YES
START
END
D
THE SYSTEM
SHUT DOWN
NO
July 30, 2008
FN6651.1