CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 70

• Manufacturer Part Number: CP2401-GQ
• Description: IC LCD DRIVER 48TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2401-GQ

• Package / Case: 48-TQFP, 48-VQFP
• Display Type: LCD
• Configuration: 128 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1860

CP2400/1/2/3
11.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTCKEY, RTCADR, and RTCDAT. These interface registers
are located on the CP2400/1/2/3 register map and provide access to the SmaRTClock internal registers listed in
Table 11.1. The SmaRTClock internal registers can only be accessed indirectly through the SmaRTClock Interface.
Table 11.1. SmaRTClock Internal Registers
11.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Register
(RTCKEY) must be written with the correct key codes, in sequence, before writes and reads to RTCADR and
RTCDAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restrictions, but the key codes
must be written in order. If the key codes are written out of order, the wrong codes are written, or an indirect register
read or write is attempted while the interface is locked, the SmaRTClock interface will be disabled, and the
RTCADR and RTCDAT registers will become inaccessible until the next system reset. Once the SmaRTClock
interface is unlocked, software may perform any number of accesses to the SmaRTClock registers until the
interface is re-locked or the device is reset. Any write to RTCKEY while the SmaRTClock interface is unlocked will
re-lock the interface.
Reading the RTCKEY register at any time will provide the SmaRTClock Interface status and will not interfere with
the sequence that is being written. The RTCKEY register description in SFR Definition 11.1 lists the definition of
each status code.
70
SmaRTClock
0x08–0x0B
0x00–0x03
Address
0x04
0x05
0x06
SmaRTClock
CAPTUREn
RTC0XCN
RTC0XCF
RTC0CN
Register
ALARMn
SmaRTClock Capture
Registers
SmaRTClock Control
Register
SmaRTClock Oscillator
Control Register
SmaRTClock Oscillator
Configuration Register
SmaRTClock Alarm
Registers
Register Name
Rev. 1.0
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
Controls the operation of the SmaRTClock State
Machine.
Controls the operation of the SmaRTClock
Oscillator.
Controls the value of the progammable
oscillator load capacitance and enables/
disables AutoStep.
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
Description