CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 77

• Manufacturer Part Number: CP2401-GQ
• Description: IC LCD DRIVER 48TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2401-GQ

• Package / Case: 48-TQFP, 48-VQFP
• Display Type: LCD
• Configuration: 128 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1860

11.2.5. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1. When the
SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if SmaRTClock
oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt and wake the device from a low power
mode. See Section “7. Interrupt Sources” on page 40 and Section “9. Power Modes” on page 49, and for more
information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
11.2.6. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during crystal
startup to determine when oscillation has started and is nearly stable. The output of this detector can be read from
the CLKVLD bit (RTX0XCN.4).
Notes: The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal oscillator, the output of
11.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every SmaRTClock
oscillator cycle. The timer has an alarm function that can be set to generate an interrupt and wake the device from
a low power mode. See Section “7. Interrupt Sources” on page 40 and Section “9. Power Modes” on page 49 more
information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after an alarm occurs. When using Auto Reset, the Alarm match value should always be set to
1 count less than the desired match value. Auto Reset can be enabled by writing a 1 to ALRM (RTC0CN.2).
11.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the timer
does not need to be stopped before reading or setting its value. The following steps can be used to set the timer
value:
The following steps can be used to read the current timer value:
11.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the ALARMn
registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers. If Auto Reset is
enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm event.
The SmaRTClock alarm event can be configured to generate a wake-up from a low power mode, or generate an
interrupt. See Section “7. Interrupt Sources” on page 40, Section “9. Power Modes” on page 49, and for more
information.
The following steps can be used to set up a SmaRTClock Alarm:
RTC0XCN.
CLKVLD is not valid.
This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure. The missing
SmaRTClock detector (CLKFAIL) should be used for this purpose.
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRTClock
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
timer.
Rev. 1.0
CP2400/1/2/3
77