ICL7106CM44Z Intersil, ICL7106CM44Z Datasheet - Page 9

• Manufacturer Part Number: ICL7106CM44Z
• Description: IC ADC 3.5 DIGIT LCD/LED 44-MQFP
• Manufacturer: Intersil

Specifications of ICL7106CM44Z

• Display Type: LCD
• Configuration: 7 Segment
• Digits Or Characters: A/D 3.5 Digits
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Interface: -

System Timing
Figure 9 shows the clocking arrangement used in the
ICL7106 and ICL7107. Two basic clocking arrangements
can be used:
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and
auto-zero (1000 to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference
de-integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33
rejection, Oscillator frequencies of 200kHz, 100kHz,
66
40kHz (2.5 readings/second) will reject both 50Hz and 60Hz
(also 400Hz and 440Hz).
1. Figure 9A. An external oscillator connected to pin 40.
2. Figure 9B. An R-C oscillator using all three pins.
2
/
3
kHz, 50kHz, 40kHz, etc. would be suitable. Note that
†
ONE INVERTER SHOWN FOR CLARITY
THREE INVERTERS
1
TYPICAL SEGMENT OUTPUT
/
3
kHz, etc. should be selected. For 50Hz
DIGITAL GROUND
0.5mA
8mA
V+
SEGMENT
9
TO
OSC 1
FROM COMPARATOR OUTPUT
40
ICL7106, ICL7107, ICL7107S
FIGURE 8. ICL7107 DIGITAL SECTION
†
TO SWITCH DRIVERS
OSC 2
V+
CLOCK
39
COUNTER
1000’s
OSC 3
b
a
COUNTER
SEGMENT
DECODE
38
e
100’s
f
7
d
g
40
40
GND ICL7107
TEST ICL7106
a
÷4
c
LATCH
b
INTERNAL TO PART
INTERNAL TO PART
c
SEGMENT
COUNTER
DECODE
e
10’s
f
7
d
FIGURE 9. CLOCK CIRCUITS
g
LOGIC CONTROL
a
c
b
39
39
R
SEGMENT
COUNTER
DECODE
e
FIGURE 9A.
FIGURE 9B.
f
1’s
7
d
g
a
c
b
38
38
500Ω
C
37
27
RC OSCILLATOR
1
÷
÷
4
4
V+
TEST
DIGITAL
GROUND
CLOCK
CLOCK
FN3082.8