LM5069MMX-1/NOPB National Semiconductor, LM5069MMX-1/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM5069MMX-1/NOPB
• Description: IC CTLR HOT SWAP 48V 10-MSOP
• Manufacturer: National Semiconductor
• Type: Hot-Swap Controllerr

Specifications of LM5069MMX-1/NOPB

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 9 V ~ 80 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• For Use With: LM5069EVAL - BOARD EVALUATION LM5069
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM5069MMX-1

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lated to reduce the load current, keeping Q1’s power from
exceeding the threshold. For proper operation of the power
limiting feature, R
iting circuit is active, the fault timer is active as described in
the Fault Timer & Restart section. Typically, power limit is
reached during startup, or if the output voltage falls due to a
severe overload or short circuit.
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM5069-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
If the application does not require use of the power limit func-
tion the PWR pin can be left open.
TURN-ON TIME
The output turn-on time depends on whether the LM5069 op-
erates in current limit, or in both power limit and current limit,
during turn-on.
A) Turn-on with current limit only: The current limit thresh-
old (I
the current limit threshold is less than the current defined by
the power limit threshold at maximum V
at the current limit threshold only during turn-on. Referring to
Figure 11a, as the load current reaches I
source voltage is controlled at V
I
the drain current reduces to its normal operating value, and
the gate is charged to approximately 12V (V
for the OUT pin voltage to transition from zero volts to V
equal to:
where C
C
maximum instantaneous power dissipated in the MOSFET is
48W. This calculation assumes the time from t1 to t2 in Figure
11a is small compared to t
current until after the output voltage has reached its final val-
ue, and PGD switches high (Figure 9). If the load draws
current during the turn-on sequence (Figure 10), the turn-on
time is longer than the above calculation, and is approximate-
ly equal to:
where R
must be set longer than t
the turn-on sequence is complete.
LIM
L
. As the output voltage reaches its final value (V
= 1000 µF, and I
LIM
) is determined by the current sense resistor (R
L
L
is the load capacitance. For example, if V
is the load resistance. The Fault Timeout Period
PWR
LIM
must be
ON
= 1A, t
ON
to prevent a fault shutdown before
, and the load does not draw any
≤
ON
150 kΩ. While the power lim-
GSL
calculates to 48 ms. The
to maintain the current at
DS
the circuit operates
LIM
GATE
, the gate-to-
). The time
SYS
DS
= 48V,
≊
SYS
S
0V)
). If
is
14
B) Turn-on with power limit and current limit: The maxi-
mum allowed power dissipation in Q1 (P
the resistor at the PWR pin, and the current sense resistor
R
threshold (I
limit threshold at maximum V
erates initially at the power limit mode when the V
high, and then transitions to current limit mode as the current
increases to I
suming the load (R
for the output voltage to reach its final value is approximately
equal to:
For example, if V
P
rent level (I
Period must be set longer than t
FET(LIM)
S
. See the Power Limit Threshold section. If the current limit
FIGURE 10. Load Draws Current During Turn-On
FIGURE 9. No Load Current During Turn-On
= 20W, t
LIM
P
) is approximately 0.42A. The Fault Timeout
LIM
) is higher than the current defined by the power
and V
ON
SYS
L
) is not connected during turn-on, the time
calculates to
= 48V, C
DS
decreases. See Figure 11ab. As-
DS
(P
L
ON
= 1000 µF, I
FET(LIM)/
≊
.
68 ms, and the initial cur-
FET(LIM)
V
SYS
) the circuit op-
LIM
) is defined by
DS
= 1A, and
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of Q1 is