LM5069MMX-1/NOPB National Semiconductor, LM5069MMX-1/NOPB Datasheet - Page 18

• Manufacturer Part Number: LM5069MMX-1/NOPB
• Description: IC CTLR HOT SWAP 48V 10-MSOP
• Manufacturer: National Semiconductor
• Type: Hot-Swap Controllerr

Specifications of LM5069MMX-1/NOPB

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 9 V ~ 80 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• For Use With: LM5069EVAL - BOARD EVALUATION LM5069
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM5069MMX-1

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If a delay is required at PGD, suggested circuits are shown in
Figure 16. In Figure 16a, capacitor C
ing edge, but not to the falling edge. In Figure 16b, the rising
edge is delayed by R
Design-in Procedure
The recommended design-in procedure is as follows:
•
•
•
•
•
Determine the current limit threshold (I
must be higher than the normal maximum load current,
allowing for tolerances in the current sense resistor value
and the LM5069 Current Limit threshold voltage. Use
equation 1 to determine the value for R
Determine the maximum allowable power dissipation for
the series pass FET (Q1), using the device’s SOA
information. Use equation 2 to determine the value for
R
Determine the value for the timing capacitor at the TIMER
pin (C
(t
turn-on time can be estimated using the equations in the
TURN-ON TIME section of this data sheet, but should be
verified experimentally. Review the resulting insertion
time, and restart timing if the LM5069-2 is used.
Choose option A, B, C, or D from the UVLO, OVLO section
of the Application Information for setting the UVLO and
OVLO thresholds and hysteresis. Use the procedure for
the appropriate option to determine the resistor values at
the UVLO and OVLO pins.
Choose the appropriate voltage, and pull-up resistor, for
the Power Good output.
FAULT
PWR
.
T
) must be longer than the circuit’s turn-on-time. The
) using equation 3. The fault timeout period
PG1
+ R
PG2
FIGURE 16. Adding Delay to the Power Good Output Pin
and C
PG
adds delay to the ris-
PG
LIM
S
, while the falling
.
). This threshold
FIGURE 15. Power Good Output
18
edge is delayed a lesser amount by R
diode across R
two edges, or a short delay at the rising edge and a long delay
at the falling edge.
PC Board Guidelines
The following guidelines should be followed when designing
the PC board for the LM5069:
•
•
•
•
•
•
Place the LM5069 close to the board’s input connector to
minimize trace inductance from the connector to the FET.
Place a small capacitor (1000 pF) directly adjacent to the
VIN and GND pins of the LM5069 to help minimize
transients which may occur on the input supply line.
Transients of several volts can easily occur when the load
current is shut off.
The sense resistor (R
and connected to it using the Kelvin techniques shown in
Figure 8.
The high current path from the board’s input to the load
(via Q1), and the return path, should be parallel and close
to each other to minimize loop inductance.
The ground connection for the various components
around the LM5069 should be connected directly to each
other, and to the LM5069’s GND pin, and then connected
to the system ground at one point. Do not connect the
various component grounds to each other through the high
current ground line.
Provide adequate heat sinking for the series pass device
(Q1) to help reduce stresses during turn-on and turn-off.
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PG2
(Figure 16c) allows for equal delays at the
S
) should be close to the LM5069,
PG2
and C
PG
. Adding a
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