ISL97673IRZ-TK Intersil, ISL97673IRZ-TK Datasheet - Page 12

• Manufacturer Part Number: ISL97673IRZ-TK
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97673IRZ-TK

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz, 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Voltage - Output: *
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• When SEL1 is high, Pins 6 and 7 Correspond to
• When SEL1 is floating and SEL2 is high, the channels
• When SEL1 is floating and SEL2 is floating, the
• When SEL1 is floating and SEL2 is low, the channels
• When SEL1 is low and SEL2 is high, this combination
• When SEL1 is low and SEL2 is floating, it is in DC
• When SEL1 is low and SEL2 is low, it is in direct PWM
Dimming Controls
The ISL97673 allow two ways of controlling the LED
current, and therefore, the brightness. They are:
There are various ways to achieve DC or PWM current
control, which will be described in the following.
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an
appropriate value for R
the maximum possible LED current:
I
1. DC current adjustment
2. PWM chopping of the LED current defined in Step 1.
LEDmax
SEL1
Float
Float
Float
High
SMBDAT and SMBCLK Accordingly. The dimming duty
cycle is controlled by the SMBus/I
and the dimming frequency is set by RFPWM.
will be in phase shift mode with fixed delay. The
dimming signal is derived from the applied PWMI
signal and the dimming frequency is set by RFPWM.
channels will be in phase shift mode with equal
phase. The dimming signal is derived from the
applied PWMI signal and the dimming frequency is
set by RFPWM.
phase shift mode is disabled. The dimming signal is
derived from the applied PWMI signal and the
dimming frequency is set by RFPWM.
is not used thus the operation will not change.
dimming mode such that the output current is
averaged in DC and is proportional to the applied
PWMI signal duty cycle.
mode such that the dimming follows directly from
the applied PWMI signal.
Low
Low
Low
=
SEL2
Float
Float
High
High
Low
Low
(
-------------------
N/A
R
401.8
SET
)
Selectable by SMBus/I
PWMI, Fixed-Delay Phase Shift PWM
PWMI, Equal-Phase Phase Shift PWM
PWMI, No-Delay PWM
Not Used
DC Current Adjustment
Direct PWM
SET
TABLE 1.
12
. This should be chosen to fix
OPERATING MODE
2
C communications
2
C Interface
(EQ. 2)
ISL97673
DC CURRENT ADJUSTMENT
Once R
through Register 0x07 (BRTDC) as Equation 3:
BRTDC can be programmed from 0 to 255 in decimal and
defaults to 255 (0xFF). If left at the default value, LED
current will be fixed at I
dynamically on the fly during operation and a “0” value
disconnects all channels.
For example, if the maximum required LED current
(I
Equation 4:
If BRTDC is set to 200 then:
PWM CONTROL
The ISL97673 provides two different PWM dimming
methods, as described in the following. Each of these
methods results in PWM chopping of the current in the
LEDs for all 6 channels to provide an average LED
current. During the On periods, the LED current will be
defined by the value of R
Equations 2 and 3. The source of the PWM signal can be
described as follows:
The default PWM dimming is in SMBus/I
methods, the average LED current of each channel is
controlled by I
Method 1 (SMBus/I
To use this mode, users need to set Register 0x01 to
0x05 with EN/PWM in logic high.
The average LED current of each channel is controlled
by the SMBus/I
where BRT is the PWM brightness level programmed in
the Register 0x00. BRT ranges from 0 to 255 in decimal
and defaults to 255 (0xFF). BRT = 0 disconnects all
channels.
I
R
I
I
I
LED
LED
1. SMBus/I
2. External signal from PWM.
LED ave
LED ave
SET
LED(max)
programmed through the SMBus/I
(
(
=
=
=
1.58x BRTDC R
1.58 200 20100
SET
401.8 0.02
)
)
=
=
) is 20mA, rearranging Equation 2 yields
is fixed, the LED DC current can be adjusted
•
I
I
(
LED
LED
⁄
2
LED
C generated 256 level duty cycle
×
×
2
⁄
C setting as:
PWM
(
BRT 255
=
and the PWM duty cycle in percent as:
⁄
20.1kΩ
SET
=
⁄
2
LEDmax
C controlled PWM)
15.7mA
SET
)
)
and BRTDC, as described in
. BRTDC can be adjusted
2
2
C.
C mode. In both
June 24, 2010
(EQ. 3)
(EQ. 4)
(EQ. 5)
(EQ. 6)
(EQ. 7)
FN7633.0