ISL97673IRZ-TK Intersil, ISL97673IRZ-TK Datasheet - Page 21

• Manufacturer Part Number: ISL97673IRZ-TK
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97673IRZ-TK

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz, 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Voltage - Output: *
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This register has two bits that control either SMBus/I
controlled or external PWM controlled PWM dimming and
a single bit that controls the BL ON/OFF state. The
remaining bits are reserved. The bit assignment is shown
in Figure 30. All other bits in the Device Control Register
will read as low unless otherwise written.
• All defined control bits return their current, latched
A value of 1 written to BL_CTL turns on the BL in 4ms or
less after the write cycle completes. The BL is
• deemed to be on when Bit 3 BL_STAT of Register 0x02
• A value of 0 written to BL_CTL immediately turns off the
• When SMBus/I
• The default value for Register 0x01 is 0x00.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of
the backlight controller’s operating state. Bit 0 is a logical
“OR” of all fault codes to simplify error detection. Not all
of the bits in this register are fault related (Bit 3 is a
simple BL status indicator). The remaining bits are
reserved and return a “0” when read. All of the bits in
RESERVED RESERVED
REGISTER 0x02
value when read.
is 1 and Register 0x09 is not 0.
BL. The BL is deemed to be off when Bit 3 BL_STAT of
Register 0x02 is 0 and Register 0x09 is 0.
Register 0x00 reflects the last value written to it
from SMBus/I
Bit 7 (R)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BIT
Bit 6 (R)
2
2
C.
C mode with DPST is selected,
FAULT/STATUS REGISTER
21
2_CH_SD
Bit 5 (R)
BIT ASSIGNMENT
FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER
THRM_SHDN
2_CH_SD
1_CH_SD
OV_CURR
BL_STAT
FAULT
1_CH_SD
Bit 4 (R)
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
= BL Status (1 = BL On, 0 = BL Off)
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
= Fault occurred (Logic “OR” of all of the fault conditions)
BL_STAT
Bit 3 (R)
2
ISL97673
C
this register are read-only, with the exception of Bit 0,
which can be cleared by writing to it.
• A Read Byte cycle to Register 0x02 indicates the
• A Read Byte cycles to Register 0x2 also returns
• 1_CH_SD returns a 1 if one or more channels have
• 2_CH_SD returns a 1 if two or more channels have
• A fault will not be reported in the event that the BL is
• When FAULT is set to 1, it will remain at 1 even if the
• The default value for Register 0x02 is 0x00.
Si Revision Register (0x03)
The Si Revision register has 3 bits that allows up to 8
silicon revisions each. In order to keep the number of
silicon revisions low, the revision field will not be updated
unless the part will make it out to the user’s factory.
Thus, if during the first silicon engineering development
process, 2 silicon spins were needed, the revision
remains as 0. All of the bits in this register are read-only.
• The default value for Register 0x03 is 0xC8.
The initial value of REV shall be 0. Subsequent values of
REV will increment by 1.
OV_CURR THRM_SHDN
Bit 2 (R)
current BL on/off status in BL_STAT (1 if the BL is on,
0 if the BL is off).
FAULT as the logical OR of THRM_SHDN, OV_CURR,
2_CH_SD, and 1_CH_SD should these events occur.
faulted out.
faulted out.
commanded on and then immediately off by the
system.
signal which sets it goes away. FAULT will be cleared
when the BL_CTL bit of the Device Control Register is
toggled or when written low. At that time, if the fault
condition is still present or reoccurs, FAULT will be
set to 1 again. BL_STAT will not cause FAULT to be
set
.
BIT FIELD DEFINITIONS
Bit 1 (R)
Bit 0 (R)
FAULT
June 24, 2010
FN7633.0