ISL97673IRZ-TK Intersil, ISL97673IRZ-TK Datasheet - Page 23

• Manufacturer Part Number: ISL97673IRZ-TK
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97673IRZ-TK

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz, 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Voltage - Output: *
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Vsc bits allow users to set 3 levels of channel
short-circuit thresholds or disable it.
The bit assignment is shown in Figure 34. The default
value for Register 0x08 is 0x1F.
Output Channel Select and Fault Readout
Register (0x09)
This register can be read or write; the bit position
corresponds to the channel. For example, Bit 0
corresponds to CH0 and Bit 4 corresponds to CH4 and so
on. Writing data to this register, it enables the channels
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
Reserved
RESERVED
Bit 7 (R/W)
REGISTER 0x09
REGISTER 0x08
BIT ASSIGNMENT
BIT ASSIGNMENT
BstSlewRate[1:0]
PWM-to-DC
DirectPWM
CH[5..0]
VSC[1..0]
FSW
Reserved
DIRECT PWM
Bit 6 (R/W)
CONFIGURATION REGISTER
OUTPUT CHANNEL REGISTER
23
CH5 = Channel 5, CH4 = Channel 4 and so
Forces the PWMI signal to directly control the current sources. Note that there is some
synchronous delay between PWMI and current sources.
Switches current sources on and varies DC level rather than PWMing.
Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength,
10 -75% drive strength, 11 to 100% drive strength.
2 levels of Switching Frequencies (0 = 1,200kHz, 1 = 600kHz)
3 levels of Short-Circuit Thresholds (0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.8V)
CH5
FIGURE 35. DESCRIPTIONS OF OUTPUT CHANNEL REGISTER
FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER
PWM-TO-DC
Bit 5 (R/W)
BIT FIELD DEFINITIONS
CH4
BSTSLEWRATE1 BSTSLEWRATE0
on
Bit 4 (R/W)
CH3
ISL97673
BIT FIELD DEFINITIONS
of interest. When reading data from this register, any
disabled channel and any faulted out channel will read as
0. This allows the user to determine which channel is
faulty and optionally not enabling it in order to allow the
rest of the system to continue to function. Additionally, a
faulted out channel can be disabled and re-enabled in
order to allow a retry for any faulty channel without
having to power-down the other channels.
The bit assignment is shown in Figure 35. The default for
Register 0x09 is 0x3F.
CH2
Bit 3 (R/W)
CH1
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
FSW
CH0
VSC1
VSC0
June 24, 2010
FN7633.0