ICE1CS02G

Manufacturer Part NumberICE1CS02G
DescriptionIC PFC CTRLR AVERAGE CURR DSO16
ManufacturerInfineon Technologies
ICE1CS02G datasheet
 


Specifications of ICE1CS02G

ModeAverage CurrentFrequency - Switching65kHz
Current - Startup1.3mAVoltage - Supply11 V ~ 25 V
Operating Temperature-40°C ~ 150°CMounting TypeSurface Mount
Package / CaseDSO-16Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesSP000444092
SP000783614
  
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Full-wave
Current Limit
Rectifier
1.0V
ISENSE
R2
1.43x
I
INDUCTOR
O P 1
R1
Figure 11
Peak Current Limit (PCL)
3.4.6
Open Loop Protection / Input Under
Voltage Protect (OLP)
Whenever VSENSE voltage falls below 0.6V, or
equivalently V
falls below 20% of its rated value, it
OUT
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.6V as shown in the
IC block diagram in Figure 2.
3.4.7
Over-Voltage Protection (OVP)
Whenever V
exceeds the value set by pin 3 (PFC
OUT
OVP), higher than 3.15V, the over-voltage protection
OVP is active as shown in Figure 8, turning off gate. In
addition, a VSENSE voltage higher than 3.15V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V
Version 1.0
3.4.8
The complete system current loop is shown in Figure
13.
Turn Off
C 2
Driver
ISENSE
ICOMP
C3
for
IN
Figure 12
It consists of the current loop block which averages the
voltage at pin 16 (PFC ISENSE), resulted from the
inductor current flowing across R1. The averaged
waveform is compared with an internal ramp in the
ramp generator and PWM block. Once the ramp
crosses the average waveform, the comparator C1
turns on the driver stage through the PWM logic block.
The Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
.
OUT
3.4.9
The compensation of the current loop is done at the pin
1 (PFC ICOMP). This is the OTA2 output and a
capacitor C3 has to be installed at this node to ground
(see Figure 13). Under normal mode of operation, this
pin gives a voltage which is proportional to the
averaged inductor current. This pin is internally shorted
to 4V in the event of IC shuts down when OLP and
UVLO occur.
3.4.10
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D
CCM PFC system is given as
D
=
OFF
From the above equation, D
12
Combi PFC/ PWM Controller
ICE1CS02
Functional Description
Complete Current Loop
L1
D1
From
Full-wave
Retifier
R7
R2
R1
PFC
Current Loop
voltage
proportional to
averaged
Inductor current
PFC
Current Loop
PWM
Compensation
Comparator
OTA2
C1
1.0mS
+/-50uA (linear range)
S2
Nonlinear
4V
Gain
Fault
Complete System Current Loop
Current Loop Compensation
Pulse Width Modulation (PWM)
V
IN
------------- -
V
OUT
is proportional to V
OFF
Vout
R3
C2
R4
GATE
Gate
Driver
Q
R
S
PWM Logic
Input From
Voltage Loop
for a
OFF
.
IN
25 July 2008