IR3503MTRPBF International Rectifier, IR3503MTRPBF Datasheet - Page 14

• Manufacturer Part Number: IR3503MTRPBF
• Description: IC CTRL XPHASE VR11.0/1 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3503MTRPBF

• Applications: Processor
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IR3503MTRPBFTR

IR3503
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is nominally
33 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping.
The output of the current sense amplifier is summed with the VDAC voltage and sent to the control IC and other
phases through an on-chip 3 k
resistor connected to the IIN pin. The IIN pins of all the phases are tied together and
the voltage on the share bus represents the average current through all the inductors and is used by the control IC for
voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to
reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
f
SW
21calibration algorithm creates ripple on IIN bus with a frequency of
in a multiphase architecture.
32
*
28
Average Current Share Loop
Current sharing between the phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the
share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and
output current. The current share amplifier is internally compensated; such that, the crossover frequency of the current
share loop is much slower than that of the voltage loop and the two loops do not interact.
IR3503 THEORY OF OPERATION
Block Diagram
The block diagram of the IR3503 is shown in figure 10.
VID Control
The control IC allows the processor voltage to be set by a parallel eight bit digital VID bus. The VID codes set the
VDAC as shown in Table 1. The VID pins require an external bias voltage and should not be floated. The VID input
comparators monitor the VID pins and control the Digital-to-Analog Converter (DAC), whose output is sent to the
VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error
amplifier and remote sense differential amplifier are post-package trimmed to achieve 0.5 % system set-point accuracy
for VID range between 1 V to 1.6 V. A set-point accuracy of ± 5 mV and ± 8 mV is achieved for VID ranges of 0.8 V-1 V
and 0.5 V-0.8 V respectively. The actual VDAC voltage does not determine the system accuracy, which has a wider
tolerance.
The IR3503 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The slew
rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID
transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush
currents in the input and output capacitors and overshoot of the output voltage.
Page 14 of 39
February 12, 2010