IR3503MTRPBF International Rectifier, IR3503MTRPBF Datasheet - Page 28

• Manufacturer Part Number: IR3503MTRPBF
• Description: IC CTRL XPHASE VR11.0/1 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3503MTRPBF

• Applications: Processor
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IR3503MTRPBFTR

DESIGN PROCEDURES - IR3503 AND IR3529 CHIPSET
IR3503 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR3503 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
the each phase converter equals the PHSOUT frequency, which is set by the external resistor R
the curve in Figure 6. The CLKOUT frequency equals the switching frequency multiplied by the phase number.
The Rosc sets the reference current used for no load offset which can be calculated by the equation shown
below:
Soft Start Capacitor C
The soft start capacitor C
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the converter
output voltage, as shown in Figure 11. After the ENABLE pin voltage rises above 0.85V, there is a soft-start delay
time TD1
time TD2 represents the time during which converter voltage rises from 0 to 1.1V
(TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time when VID
changes from boot voltage to the final voltage. The VRRDY delay time (TD5) is the time period from VR reaching
the final voltage to the VRRDY signal being issued, which is determined by the delay comparator threshold.
C
SS/DEL
= 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
Page 28 of 39
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after which the error amplifier output is released to allow the soft start of output voltage. The soft start
SS/DEL
SS/DEL
TD
TD
TD
5
programs five different time parameters. They include soft start delay time, soft
4
3
=
=
=
C
C
TD
TD
C
SS
SS
SS
/
1
DEL
2
/
/
=
ISETPT
DEL
DEL
=
I
( *
CHG
C
C
I
*
. 3
SS
*
CHG
SS
I
3 (
92
CHG
V
/
I
I
/
DEL
CHG
DAC
−
DEL
CHG
−
=
1
) 3
4 .
. 0
Rosc
1 *
1 *
−
595
−
−
1
4 .
TD
1
1 .
1 .
) 1 .
=
=
4
=
C
=
=
C
52
C
52
SS
C
SS
C
SS
52
5 .
52
SS
/
5 .
SS
/
DEL
/
DEL
/
*
5 .
5 .
/
DEL
*
DEL
52
DEL
10
10
*
*
1 *
5 .
10
10
*
1 *
−
*
−
*
6
. 0
*
4 .
6
−
0
−
V
1 .
10
6
92
6
7 .
DAC
−
−
6
.
TD
The VID sample delay time
−
February 12, 2010
1
4
1 .
IR3503
OSC
according to
(1)
(2)
(3)
(4)
(5)
(6)