IC REG/CTRLR ACPI DUAL DDR 28QFN

ISL6537ACR

Manufacturer Part NumberISL6537ACR
DescriptionIC REG/CTRLR ACPI DUAL DDR 28QFN
ManufacturerIntersil
ISL6537ACR datasheet
 


Specifications of ISL6537ACR

ApplicationsMemory, DDR/DDR2 RegulatorCurrent - Supply7mA
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case28-QFNLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Voltage - Supply-  
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Data Sheet
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
during S0/S1 and S3 states. During S0/S1 state,
DDQ
a fully integrated sink-source regulator generates an accurate
(V
/2) high current V
voltage without the need for a
DDQ
TT
negative supply. A buffered version of the V
provided as V
. A second PWM controller, which requires
REF
external MOSFET drivers, is available for regulation of the
GMCH Core voltage. An LDO controller is also integrated for
the CPU V
termination voltage regulation and the DAC.
TT
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±
2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V
TT
is within spec and operational.
All outputs, except VDAC, have undervoltage protection.
The switching regulator also has overvoltage and
overcurrent protection. Thermal shutdown is integrated.
Pinout
ISL6537A (6X6 QFN)
TOP VIEW
28
27
26
25
24
23
5VSBY
1
2
S3#
3
P12V
GND
GND
4
29
5
DDR_VTT
DDR_VTT
6
VDDQ
7
8
9
10
11
12
13
1
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V
- PWM Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V
- LDO Regulator for DAC
/2 reference is
DDQ
• ACPI Compliant Sleep State Control
• Glitch-Free Transitions During State Changes
• Integrated V
• V
PWM Controller Drives Low Cost N-Channel
DDQ
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM Controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs:
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V Supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
termination voltage
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
• OCP on the V
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
22
ACPI Compliant PCs
21
DRIVE3
• Graphics Cards - GPU and Memory Supplies
20
FB3
• ASIC Power Supplies
19
PWM4
• Embedded Processor and I/O Supplies
FB4
18
• DSP Supplies
17
COMP4
16
COMP
15
FB
14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
All other trademarks mentioned are the property of their respective owners.
ISL6537A
July 18, 2007
FN9143.5
Termination
TT
Buffer
REF
±
2% Over Temperature
Switching Regulator
DDQ
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved
DDQ
TT

ISL6537ACR Summary of contents

  • Page 1

    ... All other trademarks mentioned are the property of their respective owners. ISL6537A July 18, 2007 FN9143.5 Termination TT Buffer REF ± 2% Over Temperature Switching Regulator DDQ | Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved DDQ TT ...

  • Page 2

    ... ISL6537ACR ISL6537ACR ISL6537ACRZ (Note) ISL6537ACRZ ISL6537ACRZA (Note) ISL6537ACRZ *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

  • Page 3

    Block Diagram 180° PHASE PWM4 SHIFT COMP4 EA4 FB4 P12V EA2 DRIVE2 FB2 P12V EA3 DRIVE3 FB3 5VSBY S3# S5# FB P12V EA1 POR EA1 ACTIVE IN S3 MONITOR AND CONTROL SOFTSTART & ENABLE A SOFTSTART & ENABLE B SOFTSTART ...

  • Page 4

    Simplified Power System Diagram 3V3ATX SLP_S3 SLP_S5 Q3 V GMCH + TT_GMCH/CPU + Typical Application 3VDUAL ATX3V3 SLP_S5 SLP_S3 Q3 V GMCH TT_GMCH/CPU R9 R9 ATX3V3 Q6 V DAC R11 4 ...

  • Page 5

    ... Thermal Information Thermal Resistance (Typical, Notes 1, 2) QFN Package . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package +150° 7.0V (DC) Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp SYMBOL TEST CONDITIONS I S3# and S5# HIGH, UGATE/LGATE Open CC_S0 I S5# LOW, S3# Don’ ...

  • Page 6

    Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) PARAMETER PWM CONTROLLER GATE DRIVERS UGATE and LGATE Source UGATE and LGATE Sink VTT REGULATOR Upper Divider Impedance Lower ...

  • Page 7

    ... N-channel MOSFET. PWM4 (Pin 19) This pin provides the PWM output for the GMCH core switching regulator. Connect this pin to the PWM input of an Intersil MOSFET driver. ) DS(ON) FB4 (Pin 19) and COMP4 (Pin 17) The GMCH core switching regulator employs a single voltage control loop ...

  • Page 8

    FB2 (Pin 18) Connect the output of the V TT_GMCH/CPU this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is monitored for undervoltage events. DRIVE2 (Pin 10) This pin provides ...

  • Page 9

    SLP_S3# SLP_S5# 12V POR 12V 0V V DDQ_DDR 0V V GMCH 0V V TT_GMCH/CPU 0V V DAC 0V V DDQ_DDR V TT_DDR 0V VIDPGD (3 SOFTSTART CYCLES Soft-Start Rise Time Dependent ...

  • Page 10

    S3 sleep state. When the ISL6537A enables the V or enters S0 state from a sleep state, this short is released and the internal divide down resistors which set the V voltage ...

  • Page 11

    An internal 20μA (typical) current sink develops a voltage across R that is referenced to the OCSET converter input voltage. When the voltage across the upper MOSFET (also referenced to the converter input voltage) exceeds the ...

  • Page 12

    ATX P12V C BP GNDP 5VDUAL 5VSBY 5VSBY C BP ISL6537A UGATE Q 1 PHASE LGATE Q 2 COMP VDDQ(2) VTT( ...

  • Page 13

    The modulator transfer function is the small-signal transfer function This function is dominated OUT E/A Gain and the output filter (L and break frequency at F and a zero at ...

  • Page 14

    Component Selection Guidelines Output Capacitor Selection - PWM Buck Converter An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. ...

  • Page 15

    For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of ...

  • Page 16

    ... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...