ISL62383HRTZ Intersil, ISL62383HRTZ Datasheet - Page 17

• Manufacturer Part Number: ISL62383HRTZ
• Description: IC PWR SUPPLY CONTROLLER 28TQFN
• Manufacturer: Intersil

Specifications of ISL62383HRTZ

• Applications: Power Supply Controller
• Voltage - Supply: 5.5 V ~ 25 V
• Current - Supply: 150µA
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Resistor R
to sense the inductor current. To sense the inductor current
correctly, not only in DC operation but also during dynamic
operation, the RC network time constant R
needs to match the inductor time constant L/DCR. The value
of C
For example, if L is 1.5µH, DCR is 4.5mΩ, and R
9kΩ, the choice of C
Upon converter start-up, the C
prevent false OCP during this time, a 10µA current source
flows out of the ISEN1 pin, generating a voltage drop on the
R
resistance as R
ISEN1 pin current source will be removed.
When an OCP fault is declared, the PGOOD pin will
pull-down to 32Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage, or until V
the falling POR threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
Furthermore, Equation 9 is changed in Equation 12:
Where R
inductor current. For example, with an R
an OCP target of 10A, R
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold for more
than 2µs. The FB pin voltage is 0.6V in normal operation.
The rising over voltage threshold is typically 116% of that
value, or 1.16*0.6V = 0.696V.
When an OVP fault is declared, the PGOOD pin will pull
down with 65Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage, or until V
the falling POR threshold.
For ISL62381 and ISL62383, although the converter has
latched-off in response to an OVP fault, the LGATE gate-
driver output will retain the ability to toggle the low-side
MOSFET on and off in response to the output voltage
transversing the OVP rising and falling thresholds. The
LGATE gate-driver will turn on the low-side MOSFET to
discharge the output voltage, thus protecting the load from
C
V
R
O
SEN
OCSET1
OCSET
resistor, which should be chosen to have the same
SEN
=
-----------------------------------------
R
SENSE
is then written as Equation 10:
=
–
OCSET
OCSET
V
I
------------------------------------ -
ISEN1
OC
L
•
10μA
OCSET
R
is the series power resistor for sensing
•
SENSE
and capacitor C
DCR
=
SEN
I
L
. When PGOOD pin goes high, the
•
R
OCSET
= 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
SENSE
17
SEN
–
= 1kΩ.
10μA R
SEN
capacitor bias is 0V. To
IN
IN
form an RC network
•
SENSE
has decayed below
has decayed below
OCSET
OCSET
ISL62381, ISL62382, ISL62383
= 1mΩ and
OCSET
C
SEN
(EQ. 10)
(EQ. 12)
(EQ. 11)
is
potentially damaging voltage levels. The LGATE gate-driver
will turn off the low-side MOSFET once the FB pin voltage is
lower than the falling overvoltage threshold for more than
2µs. The falling overvoltage threshold is typically 106% of
the reference voltage, or 1.06*0.6V = 0.636V. This process
repeats as long as the output voltage fault is present,
allowing the ISL62381/3 to protect against persistent
over-voltage conditions.
For ISL62382, if OVP is detected, it simply tri-states the
PHASE node by turning UGATE and LGATE off.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold for more than
2µs. The undervoltage threshold is typically 86% of the
reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is
declared, and the PGOOD pin will pull-down with 93Ω and
latch-off the converter. The fault will remain latched until the
EN pin has been pulled below the falling enable threshold, or
if V
Programming the Output Voltage
When the converter is in regulation there will be 0.6V
between the FB and GND pins. Connect a two-resistor
voltage divider across the OUT and GND pins with the
output node connected to the FB pin as shown in Figure 27.
Scale the voltage-divider network such that the FB pin is
0.6V with respect to the GND pin when the converter is
regulating at the desired output voltage. The output voltage
can be programmed from 0.6V to 5.5V.
Programming the output voltage is written as Equation 13:
Where:
Choose R
then calculate R
Compensation Design
Figure 27shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C
integrated inside the IC that connects across the FB pin and the
V
R
OUT
BOTTOM
- V
- The voltage to which the converter regulates the FB pin
- R
- R
IN
is the V
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
connects from the FB pin to the GND pin
has decayed below the falling POR threshold.
OUT
TOP
BOTTOM
=
V
TOP
REF
is the voltage-programming resistor that connects
is the desired output voltage of the converter
=
REF
------------------------------------ -
V
V
•
OUT
first when compensating the control loop, and
REF
⎛
⎜
⎝
is the voltage-programming resistor that
1
BOTTOM
(0.6V)
+
•
–
---------------------------- -
R
R
V
BOTTOM
TOP
R
REF
TOP
according to Equation 14:
⎞
⎟
⎠
INT
is a 100pF capacitor
August 7, 2008
(EQ. 13)
(EQ. 14)
FN6665.4