ISL62383HRTZ Intersil, ISL62383HRTZ Datasheet - Page 20

• Manufacturer Part Number: ISL62383HRTZ
• Description: IC PWR SUPPLY CONTROLLER 28TQFN
• Manufacturer: Intersil

Specifications of ISL62383HRTZ

• Applications: Power Supply Controller
• Voltage - Supply: 5.5 V ~ 25 V
• Current - Supply: 150µA
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Where:
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 27:
Where:
As an example, suppose the high-side MOSFET has a total
gate charge Q
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be layed out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 21 (pins 4 and 18 for ISL62383).
This layout approach ensures that the controller does not
favor one channel over another during critical switching
decisions. Figure 30 illustrates one example of how to
achieve proper bilateral symmetry.
C
BOOT
- I
- I
- t
- t
- Q
- ΔV
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
inductor current minus 1/2 of the inductor ripple current
current plus 1/2 of the inductor ripple current
saturation
high-side MOSFET
the boot capacitor each time the high-side MOSFET is
switched on
VALLEY
PEAK
ON
OFF
g
BOOT
is the total gate charge required to turn on the
=
is the time required to drive the device into
is the time required to drive the device into cut-off
INDUCTOR
----------------------- -
ΔV
HIGH-SIDE
INDUCTOR
HIGH-SIDE
MOSFETS
is the sum of the DC component of the inductor
MOSFETS
GROUND
GROUND
, is the maximum allowed voltage decay across
VIAS TO
Q
BOOT
VIAS TO
is the difference of the DC component of the
PLANE
g
PLANE
g
, of 25nC at V
PHASE
NODE
VOUT
GND
VIN
20
GS
OUTPUT
OUTPUT
CAPACITORS
CAPACITORS
= 5V, and a ΔV
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
ISL62381, ISL62382, ISL62383
BOOT
(EQ. 27)
of
Signal Ground and Power Ground
The bottom of the ISL62381, ISL62382 and ISL62383 TQFN
package is the signal ground (GND) terminal for analog and
logic signals of the IC. Connect the GND pad of the
ISL62381, ISL62382 and ISL62383 to the island of ground
plane under the top layer using several vias for a robust
thermal and electrical conduction path. Connect the input
capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground (PGND) plane.
The following pin descriptions take ISL62381 and ISL62382
as an example.
PGND (Pin 23)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 21)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pins 4 and 5)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
LDO5 (Pin 22)
For best performance, place the decoupling capacitor very
close to the LDO5 and respective PGND pin, preferably on
the same side of the PCB as the ISL6238 IC.
EN (Pins 13 and 28) and PGOOD (Pins 1 and 8)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30)
For DCR current sensing, current-sense network, consisting
of R
line of symmetry
OCSET
PGND Plane
PHASE Planes
VOUT Planes
VIN Plane
FIGURE 30. SYMMETRIC LAYOUT GUIDE
Pin 4 (VCC2)
and C
SEN
, needs to be connected to the
and ISL62382
ISL62381
Pin 21 (VIN)
August 7, 2008
Co
Co
L2
L1
Ci
Ci
L2
L1
FN6665.4
U2
U1