ISL6504CBN Intersil, ISL6504CBN Datasheet - Page 12

• Manufacturer Part Number: ISL6504CBN
• Description: IC MULTIPLE POWER CTRLR 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6504CBN

• Applications: Power Supply Controller/Monitor
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Input: -

pins of the control IC, and connect them to ground through a
via placed close to the ground pad. Minimize any leakage
current paths from the SS node, as the internal current
source is only 10µA (typical).
A multi-layer printed circuit board is recommended.
Figure 11 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0, S1). The load transient for the
various microprocessor system’s components may require
+5VSB
+12VIN
CHF1
VOUT1
Q2
VOUT3
CHF3
FIGURE 11. PRINTED CIRCUIT BOARD ISLANDS
Q1
CBULK1
KEY
CBULK3
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
CSS
1V5SB
SS
3V3DLSB
3V3DL
3V3
ISL6504/A
12
5VSB
5VDLSB
1V2VID
GND
5VDL
C5VSB
DLA
CBULK4
+3.3VIN
CIN
VOUT4
Q4
Q3
CHF4
CHF2
ISL6504, ISL6504A
CBULK2
VOUT2
+5VIN
high quality capacitors to supply the high slew rate (di/dt)
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
Also, during the transition between active and sleep states
on the 3.3V
short interval of time during which none of the power pass
elements are conducting - during this time the output
capacitors have to supply all the output current. The output
voltage drop during this brief period of time can be easily
approximated with the following formula:
∆V
ESR
I
C
t
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an ISL6504/A application must have
a sufficiently low ESR so as not to allow the input voltage to
dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6504/A’s regulation levels could have as
a result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, such phenomena could be responsible for the
5V
regulation. The solution to such a potential problem is using
larger input capacitors with a lower total combined ESR.
Transistor Selection/Considerations
The ISL6504/A usually requires one P-Channel (or bipolar
PNP), two N-Channel MOSFETs, and one bipolar NPN
transistors.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator or an ON/OFF switching element is
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
∆
OUT
t
P
V
OUT
- active-to-sleep or sleep-to-active transition time (10µs typ.)
LINEAR
SB
OUT
OUT
OUT
- output current during transition
voltage drooping excessively and affecting the output
- output capacitor bank capacitance
=
- output voltage drop
- output capacitor bank ESR
I
=
OUT
DUAL
I
O
×
×
(



/3.3V
V
ESR
IN
–
SB
OUT
V
OUT
and 5V
+
)
--------------- -
C
OUT
t
t
DUAL



, where
outputs, there is a
April 13, 2004
FN9062.2