ISL6504CBN Intersil, ISL6504CBN Datasheet - Page 8

• Manufacturer Part Number: ISL6504CBN
• Description: IC MULTIPLE POWER CTRLR 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6504CBN

• Applications: Power Supply Controller/Monitor
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Input: -

well as all the control and monitoring functions necessary for
complete ACPI implementation.
Initialization
The ISL6504/A automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V
3.3V
after exceeding POR threshold.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3V
highlight the only difference between the ISL6504 and
ISL6504A. The internal circuitry does not allow the transition
from an S3 (suspend to RAM) state to an S4/S5 (suspend to
disk/soft off) state or vice versa. The only ‘legal’ transitions
are from an active state (S0, S1) to a sleep state (S3, S5)
and vice versa.
Functional Timing Diagrams
Figures 4 (ISL6504), 5 (ISL6504A), and 6 are timing diagrams,
detailing the power up/down sequences of all the outputs in
response to the status of the sleep-state pins (S3, S5), as well
as the status of the input ATX supply. Not shown in these
diagrams is the deglitching feature used to protect against false
sleep state tripping. Both S3 and S5 pins are protected against
noise by a 2µs filter (typically 1–4µs). This feature is useful in
noisy computer environments if the control signals have to
travel over significant distances. Additionally, the S3 pin
features a 200µs delay in transitioning to sleep states. Once the
S3 pin goes low, an internal timer is activated. At the end of
the 200µs interval, if the S5 pin is low, the ISL6504/A
switches into S5 sleep state; if the S5 pin is high, the
ISL6504/A goes into S3 sleep state.
NOTE: Combination Not Allowed.
S5
1
1
0
0
0
DUAL
DUAL/SB
TABLE 1. 5V
S3
/3.3V
1
0
1
0
0
and 5V
3.3VDL/SB
SB
SB
DUAL
3.3V
3.3V
3.3V
3.3V
and 1.5V
input supply voltage, initiating
DUAL
Note
OUTPUT (V
outputs. The last two lines
SB
5VDL
8
5V
5V
0V
5V
soft-start operation shortly
OUT4
S0/S1/S2 States (Active)
S3
Maintains Previous State
S4/S5 (ISL6504)
S4/S5 (ISL6504A)
) TRUTH TABLE
COMMENTS
ISL6504, ISL6504A
3V3DLSB
3V3DLSB
5VDLSB
5V, 12V
1V2VID
3.3V, 5V
5VDLSB
1V5SB
3.3V, 5V
FIGURE 4. 5V
3V3DL
FIGURE 5. 5V
5VSB
3V3DL
3.3V,
5VSB
5VDL
DLA
5VSB
5VDL
DLA
DLA
S3
S5
FIGURE 6. 1.5V
S3
S5
S3
S5
DIAGRAM; ISL6504
DIAGRAM; ISL6504A
DUAL
DUAL
SB
AND 3.3V
AND 3.3V
, AND 1.2V
DUAL
DUAL
VID
/3.3V
/3.3V
TIMING DIAGRAM
SB
SB
TIMING
TIMING
April 13, 2004
FN9062.2