ISL6505CB-T Intersil, ISL6505CB-T Datasheet - Page 10

• Manufacturer Part Number: ISL6505CB-T
• Description: IC MULTIPLE POWER CTRLR 20-SOIC
• Manufacturer: Intersil

Specifications of ISL6505CB-T

• Applications: Power Supply Controller/Monitor
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 6mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Input: -

supported. 3.3V
up right after bias voltage surpasses POR level (but if LAN =
GND, then V
ramp, along with V
During sleep-to-active state transitions from conditions
where the 5V
transition, or simple power-up sequence directly into active
state), the circuit goes through a quasi soft-start, the
5V
the NMOS FET connected between it and the 5V ATX.
Figure 9 exemplifies this start-up case. 5V
present when the main ATX outputs are turned on, at time
T0. As a result of +5V
capacitors charge up through the body diode of Q5 (see
Typical Application). At time T1, all main ATX outputs exceed
the ISL6505’s undervoltage thresholds, and the internal
50ms (typical) timer is initiated. At T2, the time-out initiates a
soft-start, and the 1.2V voltage ID output is ramped-up,
reaching regulation limits at time T3. Simultaneous with the
beginning of this ramp-up, at time T2, the DLA pin is
released, allowing the pull-up resistor to turn on Q3 and Q5,
and bring the 5V
T3, as the SS voltage reaches 3.0V, the soft-start capacitor
is quickly discharged down to approximately 2.7V, where it
remains until a valid sleep state request is received from the
system.
+5V
0V
0V
DUAL
SB
FIGURE 9. SOFT-START INTERVAL IN ACTIVE STATE
T0
VOLTAGES
OUTPUT
(1V/DIV)
output being pulled high through the body diode of
INPUT VOLTAGES
T1
V
V
OUT1
OUT1
OUT3
DUAL
+3.3V
(2V/DIV)
+5V
+12V
DUAL
DUAL
(LAN = 5V)
(3.3V
IN
output will not come up until the soft-start
OUT2
output is initially GND (such as S5 to S0
IN
IN
/3.3V
IN
DUAL
output in regulation. Shortly after time
; see Figure 9).
ramping up, the 5V
/3.3V
SB
T2
10
TIME
and V
SB
SOFT-START
DLA PIN
(2V/DIV)
V
OUT4
(1V/DIV)
)
OUT1
(5V
T3
V
V
DUAL
OUT1
OUT2
outputs will come
SB
DUAL
)
(LAN = GND)
(1.2V
is already
VID
output
)
ISL6505
Fault Protection
All of the outputs are monitored against undervoltage events.
A severe overcurrent caused by a failed load on any of the
outputs, would, in turn, cause that specific output to
suddenly drop. If any of the output voltages drops below 80%
(typical) of their set value, such event is reported by having
the FAULT pin pulled to 5V. Additionally, exceeding the
maximum current rating of an integrated regulator (output
with pass transistor on-chip) can lead to output voltage
drooping; if excessive, this droop can ultimately trip the
undervoltage detector and send a FAULT signal to the
computer system.
A FAULT condition occurring on an output when controlled
through an external pass transistor will only set off the
FAULT flag, and it will not shut off or latch off any part of the
circuit. A FAULT condition occurring on an output controlled
through an internal pass transistor (1V2VID only), will set off
the FAULT flag, and it will shut off the respective faulting
regulator (1V2VID only). If shutdown or latch off of the entire
circuit is desired in case of a fault, regardless of the cause,
this can be achieved by externally pulling or latching the SS
pin low. Pulling the SS pin low will also force the FAULT pin
to go low and reset any internally latched-off output.
Special consideration is given to the initial start-up
sequence. If, following a 5V
or 3.3V
an undervoltage event before the end of the second soft-
start ramp, then the FAULT output goes high and the entire
IC latches off. Latch-off condition can be reset by cycling the
bias power (5V
the 3.3V
handled according to the description found in the second
paragraph under the current heading.
Another condition that could set off the FAULT flag is chip
overtemperature. If the ISL6505 reaches an internal
temperature of 140
chip continues to operate until the temperature reaches
155
takes place. Operation resumes only after powering down
the IC (to create a 5V
(assuming the cause of the fault has been removed; if not, as
it heats up again, it will repeat the FAULT cycle).
In ISL6505 applications, loss of the active ATX output (3V3
or 5V, as detected by the on-board voltage monitor) during
active state operation causes the chip to switch to S5 sleep
state, in addition to reporting the input UV condition on the
FAULT pin. Exiting from this forced S5 state can only be
achieved by returning the faulting input voltage above its UV
threshold, by resetting the chip through removal of 5V
bias voltage, or by bringing the SS pin at a potential lower
than 0.8V.
o
C (typical), when unconditional shutdown of all outputs
DUAL
DUAL
/3.3V
/3.3V
SB
). Undervoltage events on the V
SB
o
SB
C (typical), the FAULT flag is set, but the
outputs is ramped up and is subject to
SB
outputs at any other times are
POR event) and a start-up
SB
POR event, any of the V
OUT1
SB
OUT1
and