ISL6505CB-T Intersil, ISL6505CB-T Datasheet - Page 8

• Manufacturer Part Number: ISL6505CB-T
• Description: IC MULTIPLE POWER CTRLR 20-SOIC
• Manufacturer: Intersil

Specifications of ISL6505CB-T

• Applications: Power Supply Controller/Monitor
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 6mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Input: -

The internal circuitry does not allow the transition from an
S4/S5 (suspend to disk/soft off) state to an S3 (suspend to
RAM) state; however, it does allow the transition from S3 to
S4/S5. The only ‘legal’ transitions are from an active state
(S0, S1) to a sleep state (S3, S5) and vice versa.
NOTE: Combination Not Allowed.
NOTE: Combination Not Allowed.
Functional Timing Diagrams
Figures 4 (EN5 = low), 5 (EN5 = high), and 6 are timing
diagrams, detailing the power up/down sequences of all the
outputs in response to the status of the sleep-state pins (S3,
S5), as well as the status of the input ATX supply. Not shown in
these diagrams is the deglitching feature used to protect
against false sleep state tripping. Both S3 and S5 pins are
protected against noise by a 2µs filter (typically 1–4µs). This
feature is useful in noisy computer environments if the control
signals have to travel over significant distances. Additionally, the
S3 pin features a 200µs delay in transitioning to sleep states.
Once the S3 pin goes low, an internal timer is activated. At the
end of the 200µs interval, if the S5 pin is low, the ISL6505
switches into S5 sleep state; if the S5 pin is high, the
ISL6505 goes into S3 sleep state.
The shaded column in Figures 4 and 5 highlights the
difference on the 5VDLSB and 5VDL pins for the two EN5
states.
S5
S5
TABLE 1. 5V
1
1
0
0
0
1
1
1
0
0
0
TABLE 2. V
S3
S3
1
0
1
0
0
1
0
0
1
0
0
TRUTH TABLE
DUAL
3.3VDL/SB
OUT1
V
3.3V
3.3V
3.3V
3.3V
1.5V
1.5V
1.5V
OUT1
0V
0V
OUTPUT (V
AND 1V2VID (V
Note
Note
1V2VID
5VDL
1.2V
8
0V
0V
5V
5V
0V
5V
0V
0V
OUT4
) AND 3.3VDL/SB (V
OUT2
S0/S1/S2 States (Active)
S3
Maintains Previous State
S4/S5 (EN5 = GND)
S4/S5 (EN5 = open/5V)
S0/S1/S2 States (Active)
S3 (LAN = GND)
S3 (LAN = open/5V)
Maintains Previous State
S4/S5 (LAN = GND)
S4/S5 (LAN = open/5V)
) TRUTH TABLE
COMMENTS
COMMENTS
OUT3
)
ISL6505
(LAN=5V)
3V3DLSB
3V3DLSB
5V, 12V
1V2VID
5VDLSB
3.3V, 5V
V
5VDLSB
3.3V, 5V
V
FIGURE 6. V
FIGURE 4. 5V
FIGURE 5. 5V
5VSB
3V3DL
OUT1
3V3DL
OUT1
3.3V,
5VSB
5VDL
DLA
5VSB
5VDL
DLA
DLA
S3
S5
S3
S5
S3
S5
(LAN=GND)
DIAGRAM; EN5 = GND
THE DEPENDENCE OF V
STATE OF LAN PIN)
DIAGRAM; EN5 = 5V/OPEN
OUT1
DUAL
DUAL
AND 1.2V
AND 3.3V
AND 3.3V
VID
DUAL
DUAL
TIMING DIAGRAM (NOTE
/3.3V
/3.3V
OUT1
SB
SB
ON THE LOGIC
TIMING
TIMING