ISL6569CRZ-T Intersil, ISL6569CRZ-T Datasheet - Page 10

• Manufacturer Part Number: ISL6569CRZ-T
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6569CRZ-T

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: Yes
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Current Sensing
During the forced off time following a PWM transition low, the
controller senses channel load current by sampling the
voltage across the lower MOSFET r
referenced amplifier, internal to the ISL6569, connects to the
PHASE node through a resistor, R
R
of the lower MOSFET while it is conducting. The resulting
current into the ISEN pin is proportional to the channel
current, I
sufficient settling time every switching cycle. The sampled
current is used for channel-current balance, load-line
regulation, overcurrent protection, and module current
sharing.
The circuitry shown in Figure 4 represents channel-1 of a
two channel converter. This circuitry is repeated for
channel-2 of the converter. From Figure 4, the following
equation for channel-1 sampled current, I
where I
If r
sense resistor in series with the lower MOSFET source can
serve as a sense element.
Channel-Current Balance
The sampled current from both channels, I
to gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are averaged. The resulting average
current, I
demand on the converter and the appropriate level of
channel current. Using Figures 4 and 5, the average current
is defined as
where I
The average current is then subtracted from the individual
channel sample currents. The resulting error current, I
then filtered before it adjusts V
signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any unbalance and drives
the error current toward zero. Figure 5 illustrates Intersil’s
patented current balance method as implemented on one
channel of a multi-phase converter.
I
I
I
1
AVG
AVG
ISEN
DS(ON)
=
I
L1
=
=
is equivalent to the voltage drop across the r
L1
OUT
I
--------------- -
I
-------------
r
----------------------
L
AVG
1
OUT
DS ON
R
. The ISEN current is then sampled and held after
2
is half of the total load current.
+
2
sensing is not desired, an independent current-
ISEN
I
(
is the total load current.
2
, provides a measure of the total load current
r
----------------------
DS ON
R
)
ISEN
(
)
10
COMP
ISEN
DS(ON)
. The modified V
. The voltage across
1
, is derived
1
. A ground-
and I
2
, is used
DS(ON)
COMP
(EQ. 3)
(EQ. 4)
ER
, is
ISL6569
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided.
Resulting in a cost-effective and easy to implement solution
relative to single-phase conversion. Channel current balance
insures the thermal advantage of multi-phase conversion is
realized. Heat dissipation is spread over multiple channels
and a greater area than single phase approaches.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one channel may be able to cool
more effectively than the other due to nearby air flow or heat
sinking components. The other channel may have more
difficulty cooling with comparatively less air flow and heat
sinking. The hotter channel may also be located close to
other heat-generating components tending to drive it’s
temperature even higher. In these cases, the proper
selection of the current sense resistors (R
introduces channel current unbalance into the system.
Increasing the value of R
decreasing it in the hotter channel moves both channels into
thermal balance at the expense of current balance.
Voltage Regulation
The output of the error amplifier, V
sawtooth waveform to modulate the pulse width of the PWM
signals. The PWM signals control the timing of the Intersil
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
amplifier determine the voltage level of V
and external circuitry which control voltage regulation is
illustrated in Figure 6.
V
FIGURE 5. CHANNEL-1 PWM FUNCTION AND
COMP
CURRENT-BALANCE ADJUSTMENT
+
I
ER
-
+
f(jω)
I
1
-
I
AVG
SAWTOOTH SIGNAL
ISEN
÷
in the cooler channel and
2
COMP
+
-
, is compared to the
COMP
ISEN
Σ
. The internal
December 29, 2004
in Figure 4)
PWM1
I
FN9085.7
2