ISL6569CRZ-T Intersil, ISL6569CRZ-T Datasheet - Page 17

• Manufacturer Part Number: ISL6569CRZ-T
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6569CRZ-T

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: Yes
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Balance). In this case, chose a new, smaller value of R
for the affected phase. Choose R
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
In Equation 20, make sure that ∆T
rise above the ambient temperature, and ∆T
temperature rise above the ambient temperature. While a
single adjustment according to Equation 20 is usually
sufficient, it may occasionally be necessary to adjust R
two or more times to achieve perfect thermal balance between
both channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R
Its value depends on the desired full-load droop voltage
(V
ISEN resistor, the load-line regulation resistor is as shown
in Equation 21.
If one or both of the ISEN resistors was adjusted for thermal
balance, as in Equation 20, the load-line regulation resistor
should be selected according to Equation 22. Where I
the full-load operating current and R
resistor connected to the n
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy during the interval of time after
the beginning of the transient until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response leaving the output capacitor bank to
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V
their capacitance, ESR, and ESL (equivalent series
inductance).
R
R
R
ISEN 2 ,
FB
FB
DROOP
=
=
V
------------------------ -
--------------------------------
I
50 10
FL
V
=
DROOP
in Figure 6). If Equation 19 is used to select each
DROOP
×
r
R
MAX
DS ON
ISEN
–
(
6
. Capacitors are characterized according to
∆T
----------
∆T
)
∑
n
2
1
R
ISEN n ( )
th
17
ISEN pin.
ISEN,2
2
is the desired temperature
ISEN(n)
in proportion to the
1
is the ISEN
is the measured
FB
in Figure 6.
(EQ. 20)
(EQ. 21)
(EQ. 22)
ISEN
ISEN
FL
is
ISL6569
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance, but limited
high-frequency performance. Minimizing the ESL of the high-
frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I
are selected, the maximum allowable ripple voltage,
V
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆V
Equation 26 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 25
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
∆V
L
L
L
PP(MAX)
≤
≤
≥
MAX
≈
4CV
---------------- ∆V
(
----------------- ∆V
(
(
2.5
(
∆I
(
∆I
ESR
ESL
. This places an upper limits on inductance.
)
)
) C
O
2
2
)
, determines the lower limit on the inductance.
)


--------------------------------------------------------- -
di
---- -
dt
V
MAX
IN
f
MAX
+
S
C,PP
(
MAX
V
–
ESR
IN
2V
–
–
V
∆I ESR
(ESR). Thus, once the output capacitors
∆I ESR
.
OUT
PP MAX
) ∆I
(
(
(
 V

OUT
)
)
)


V
IN
–
V
O


December 29, 2004
(EQ. 23)
(EQ. 24)
(EQ. 25)
(EQ. 26)
FN9085.7