ISL6326CRZ-T Intersil, ISL6326CRZ-T Datasheet - Page 24

• Manufacturer Part Number: ISL6326CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where V
is the resistor between the IDROOP pin and GND, I
the total output current of the converter, R
resistor connected to the ISEN+ pin, N is the active channel
number, and R
element, either the DCR of the inductor or R
depending on the sensing method.
The resistor from the IDROOP pin to GND should be chosen
to ensure that the voltage at the IDROOP pin is less than 2V
under the maximum load current.
If the IDROOP pin is not used, tie it to GND.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following sections. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts for all common
microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis, which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15A and 20A.
All surface-mount designs will tend toward the lower end of
this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In
cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r
continuous output current; I
IDROOP
DS(ON)
X
is the voltage at the IDROOP pin, R
is the resistance of the current sense
). In Equation 24, I
P-P
24
is the peak-to-peak inductor
M
is the maximum
ISEN
SENSE
is the sense
LOAD
IDROOP
is
ISL6326
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
f
and the end of the lower-MOSFET conduction interval
respectively as shown in Equation 25:
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
UPPER MOSFET POWER CALCULATION
In addition to r
upper-MOSFET losses are due to currents conducted
across the input voltage (V
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times the lower-MOSFET body-diode
reverse-recovery charge (Q
r
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET’s
reverse-recovery charge (Q
has fully commutated to the upper MOSFET before the
lower-MOSFET’s body diode can draw all of Q
P
P
P
P
S
DS(ON)
LOW,2
LOW 1
LOW 2
UP 1 ,
UP 2 ,
and the length of dead times, t
,
,
≈
≈
.
V
V
conduction loss.
=
=
IN
IN
r
V
⎛
⎝
⎛
⎜
⎝
DS ON
D ON
I
----- -
N
I
----- -
N
M
M
(
DS(ON)
(
+
–
I
--------- -
I
--------- -
)
P-P
P-P
)
2
2
f
S
⎛
⎜
⎝
⎞ t
⎠
⎞ t
⎟
⎠
I
----- -
N
M
⎛
⎝
⎛
⎜
⎝
⎛
⎜
⎝
losses, a large portion of the
I
----- -
----
⎞
⎟
⎠
N
----
2
M
2
2
1
2
⎞
⎟
⎠
⎞
⎟
⎠
(
M
+
1 d
f
f
S
S
IN
, V
I
--------- -
–
P-P
rr
rr
2
UP,2
) during switching. Since a
) and the upper MOSFET
). Since the inductor current
D(ON)
2
)
⎞ t
⎠
. In Equation 27, the
+
d1
.
d1
I
---------------------------------- -
L(P-P)
and t
+
the switching frequency,
⎛
⎜
⎝
12
I
----- -
N
(
M
1 d
d2
–
UP,1
–
1
, at the beginning
I
--------- -
P-P
and the
2
)
.
OUT
⎞
⎟
⎠
2
rr
t
, it is
d2
LOW,1
/V
May 5, 2008
IN
(EQ. 24)
(EQ. 25)
(EQ. 26)
(EQ. 27)
FN9262.1
); and
and