ISL6326CRZ-T Intersil, ISL6326CRZ-T Datasheet - Page 27

• Manufacturer Part Number: ISL6326CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The first step is to choose the desired bandwidth, f
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f
higher if desired. Choosing f
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 36, R
compensation components are then selected.
In Equation 36, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
signal amplitude as described in “Electrical Specifications”
on page 7.
R
C
C
R
C
FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED
1
1
2
C
C
=
=
=
=
=
C
R
R
---------------------------------------- -
------------------------------------------------------------------- -
(
-------------------------------------------------------------------- -
0.75 V
------------------------------------------------------------------- -
(
2π
1
1
0.75V
2π
V
FB
LC C ESR
PP
)
)
2
---------------------------------------- -
2
–
R
f
⎛
⎝
f
LC C ESR
0
IN
0
2π
FB
IN
f
C ESR
f
CONVERTER WITHOUT LOAD-LINE
REGULATION
HF
(
0.75V
HF
⎞
⎠
⎛
⎝
FB
(
–
⎛
⎝
2πf
2πf
2
f
0
LCR
LCR
is selected arbitrarily. The remaining
(
HF
f
R
HF
)
HF
IN
FB
R
)
C
LCR
FB
LC 1
FB
LC 1
)
C
V
2
V
–
–
C
P-P
FB
P-P
C
⎞
⎠
⎞
⎠
HF
27
HF
to be lower than 10f
HF
IDROOP
. This pole can be used for
COMP
VDIFF
= 10f
FB
P-P
0
, but it can be
is the sawtooth
0
0
, of the
(EQ. 36)
can
ISL6326
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI; the load-current slew rate, di/dt; and the
maximum allowable output voltage deviation under transient
loading, ΔV
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
in Equation 37:
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I
output capacitors are selected, the maximum allowable
ripple voltage, V
inductance.
ΔV
≈
(
ESL
)
MAX
di
---- -
dt
+
(
. Capacitors are characterized according to
MAX
ESR
P-P(MAX)
.
) ΔI
, determines the lower limit on the
C(P-P)
(ESR). Thus, once the
May 5, 2008
(EQ. 37)
FN9262.1