LTC3719EG Linear Technology, LTC3719EG Datasheet - Page 21

IC SW REG SYNC STEP-DOWN 36-SSOP

LTC3719EG

Manufacturer Part Number
LTC3719EG
Description
IC SW REG SYNC STEP-DOWN 36-SSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC3719EG

Applications
Controller, AMD Opteron™
Voltage - Input
4 ~ 36 V
Number Of Outputs
1
Voltage - Output
0.8 ~ 1.55 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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APPLICATIO S I FOR ATIO
The loop filter components (C
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
acquires lock. Typically R
0.1 F.
Minimum On-Time Considerations
Minimum on-time, t
that the LTC3719 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3719 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC3719 is generally less
than 200ns. However, as the peak sense voltage de-
creases, the minimum on-time gradually increases. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger ripple current and voltage ripple.
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I
t
ON MIN
V f
LP
V
IN
OUT
and R
U
ON(MIN)
LP
U
LP
, is the smallest time duration
determine how fast the loop
OUT(MAX)
=10k and C
LP
, R
W
LP
at V
) smooth out the
IN(MAX)
LP
is 0.01 F to
U
.
FCB Pin Operation
The following table summarizes the possible states avail-
able on the FCB pin:
Table 2
FCB Pin
0.65V < V
> 4.8V
Active Voltage Positioning
Active voltage positioning can be used to minimize peak-
to-peak output voltage excursion under worst-case tran-
sient loading conditions. The open-loop DC gain of the
control loop is reduced depending upon the maximum
load step specifications. Active voltage positioning can
easily be added to the LTC3719 by loading the I
a resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage of the error
amplifier, or 1.2V (see Figure 7).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can
be reduced for a particular application. A complete
explanation is included in Design Solutions 10 or the
LTC1736 data sheet. (See www.linear-tech.com)
0V to 0.55V
Figure 7. Active Voltage Positioning Applied to the LTC3719
FCB
< 4.3V (typ)
INTV
CC
R
R
T2
T1
R
C
C
C
Condition
Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
I
TH
LTC3719
3719 F08
LTC3719
TH
sn3719 3719fs
pin with
21

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