ISL6334DIRZ-T Intersil, ISL6334DIRZ-T Datasheet
ISL6334DIRZ-T
Specifications of ISL6334DIRZ-T
Related parts for ISL6334DIRZ-T
ISL6334DIRZ-T Summary of contents
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... Pb-Free (RoHS Compliant) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008-2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6334D ...
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... Ordering Information PART NUMBER (Note) ISL6334DIRZ 6334D IRZ ISL6334DCRZ 6334D CRZ NOTES: 1. Add “-T” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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ISL6334D Block Diagram VDIFF RGND - X1 + VSEN SOFT-START + OVP - FAULT LOGIC +175mV SS VID7 VID6 VID5 DYNAMIC VID4 VID VID3 D/A VID2 VID1 VID0 DAC OFS OFFSET REF FB COMP 1.11V + OCP - IMON 1.11V ...
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Typical Application: 4-Phase VR with PSI# and No Droop +5V COMP VCC DAC FB VDIFF VSEN PWM1 RGND ISEN1- EN_VTT VTT ISEN1+ VR_RDY VID7 ISL6334D ISL6334 VID6 VID5 VID4 PWM2 VID3 VID2 ISEN2- VID1 ISEN2+ VID0 PSI# VR_FAN PWM3 ISEN3- ...
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Typical Application - 4-Phase Couple Inductor VR with 2-Phase PSI# and No Droop +5V COMP VCC FB VDIFF VSEN RGND ISEN1+ EN_VTT VTT ISEN1- VR_RDY VID7 VID6 ISL6334D ISL6334 VID5 VID4 VID3 VID2 ISEN3- VID1 ISEN3+ VID0 PSI# ISEN2+ VR_FAN ...
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... Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature ISL6334DCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6334DIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. ...
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Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS Pin OSCILLATORS Accuracy of Switching Frequency Setting Adjustment ...
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Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued) PARAMETER THERMAL MONITORING AND FAN CONTROL TM Input Voltage for VR_FAN Trip TM Input ...
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... PWM1, PWM2, PWM3, PWM4 - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM2, PWM3 and PWM4. Tie PWM2 to VCC to configure for 1-phase operation. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation ...
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For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, R The voltage across the sense capacitor is proportional to ...
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... Figure 21 shows the single phase input-capacitor RMS current for comparison. PWM Modulation Scheme The ISL6334D adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads ...
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... The matching driver's internal PWM resistor divider can further raise the PWM potential, but not lower it below the level set by the controller IC. Therefore, the controller's PWM outputs are directly compatible with Intersil drivers that require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM signal amplitudes are generally incompatible. ...
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... Channel current balance is achieved by comparing the sensed current of each channel to the ) close to 27ns. average current to make an appropriate adjustment to the T PWM duty cycle of each channel with Intersil’s patented current-balance method. Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good (EQ. 6) current balance, the power loss is equally dissipated over multiple devices and a greater area ...
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... The output of the error amplifier, V COMP sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry, which control voltage regulation, are illustrated in Figure 6. ...
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TABLE 2. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
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TABLE 2. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
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... POR level before the ISL6334D becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6334D with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR ...
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ISL6334D INTERNAL CIRCUIT POR ENABLE COMPARATOR CIRCUIT + - 0.875V + - 0.875V SOFT-START AND FAULT LOGIC FIGURE 8. POWER SEQUENCING USING THRESHOLD SENSITIVE ENABLE (EN) FUNCTION Soft-Start ISL6334D based VR has 4 periods during soft-start, as shown in Figure ...
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... At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns). This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC plus 75mV, PWM signals enter a high-impedance state ...
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OUTPUT CURRENT 0A OUTPUT VOLTAGE 0V 2ms/DIV FIGURE 11. OVERCURRENT BEHAVIOR IN HICCUP MODE 500kHz ...
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TM 0.451*Vcc 0.391*Vcc 0.333*Vcc VR_FAN VR_HOT FIGURE 14. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE Based on the NTC temperature characteristics and the desired threshold of the VR_HOT signal, the pull-up resistor RTM1 of TM pin is ...
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... TC2 power converter assumed that the reader is familiar with many of the basic skills and techniques referenced in the (EQ. 20) following. In addition to this guide, Intersil provides complete reference designs, which include schematics, bills of materials, and example board layouts for all common microprocessor applications. ...
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MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET ...
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DC resistance of the current sense element may be changed according to the operational temperature Equation 27 should be the maximum DC X resistance of the current sense element at the all operational ...
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The capacitors selected must have sufficiently low ESL and ESR so that the total output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount, ...
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0.5 I L(P-P) L(P- 0. 0.75 I L(P-P) O L(P-P) 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V O/ FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ...