ISL6263BHRZ Intersil, ISL6263BHRZ Datasheet
ISL6263BHRZ
Specifications of ISL6263BHRZ
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ISL6263BHRZ Summary of contents
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... PART NUMBER PART (Notes 2, 3) MARKING TEMP (°C) ISL6263BHRZ ISL6263 BHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5 ISL6263BHRZ-T ISL6263 BHRZ -10 to +100 32 Ld 5x5 QFN (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb- ...
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Block Diagram VDD V REF + 1.545V − ↓ ↓ VSS 1:1 RBIAS OCSET − OCP VSUM + + DFB − DROOP VO VSEN RTN VDIFF VID0 VID1 VID2 VID DAC DVID VID3 ↓ VID4 SOFT FIGURE ...
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Simplified Application Circuit for DCR Current Sensing C VDD R RBIAS RBIAS C SOFT SOFT PGOOD R IMON IMON C IMON VID<0:4> VR_ON AF_EN FDE V VSEN CC_SNS V RTN SS_SNS FSET FSET C COMP1 COMP R ...
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Simplified Application Circuit for Resistive Current Sensing C VDD R RBIAS RBIAS C SOFT SOFT PGOOD R IMON IMON C IMON VID<0:4> VR_ON AF_EN FDE V VSEN CC_SNS V RTN SS_SNS FSET FSET C COMP1 COMP R ...
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... Junction Temperature Range .-55°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range -10°C to +100°C VIN to VSS +5V to +25V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ± ...
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Electrical Specifications These specifications apply for +25° -10°C to +100°C. (Continued) PARAMETER PWM Nominal Frequency Frequency Range Audio Filter Frequency AMPLIFIERS Error Amplifier DC Gain (Note 7) Error Amplifier Gain-Bandwidth Product (Note 7) Error Amp ...
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Electrical Specifications These specifications apply for +25° -10°C to +100°C. (Continued) PARAMETER POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current Overvoltage Threshold (VO-VSOFT) Severe Overvoltage Threshold OCSET Reference Current OCSET Voltage Threshold ...
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Functional Pin Descriptions RBIAS (Pin 1) - Sets the internal 10µ Connect a 150kΩ ±1% resistor from RBIAS to VSS. SOFT (Pin 2) - Sets the output voltage slew-rate. Connect an X5R or X7R ceramic capacitor from SOFT to VSS. ...
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... ISL6263B Theory of Operation 3 The R Modulator V CCGFX The heart of the ISL6263B is Intersil’s Robust-Ripple- VID0 (V) Regulator ( fixed frequency PWM control, and variable frequency 0 1.28750 hysteretic control that will simultaneously affect the PWM switching frequency and PWM duty cycle in response to 1 1.26175 input voltage and output load transients. ...
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VR_ON 90% ~100µ SOFT CCGFX PGOOD 13 SWITCHING CYCLES FIGURE 4. ISL6263B START-UP TIMING Static Regulation The V output voltage will be regulated to the value set CCGFX by the VID inputs per Table 2. A true differential ...
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OCP + DROOP + − + Σ − VDIFF FIGURE 5. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH GPU SOCKET KELVIN SENSING AND INDUCTOR DCR CURRENT SENSING Smooth mode transitions are facilitated by the R which correctly ...
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ISL6263B will latch UGATE and PGOOD low but unlike other protective faults, LGATE remains high until the voltage between VO and VSS falls below approximately 0.77V, at which time LGATE is pulled low. The LGATE pin will continue to switch ...
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The minimum value of the bootstrap capacitor can be calculated using Equation 3: Q GATE ≥ C ----------------------- - BOOT ΔV BOOT where Q is the amount of gate charge required to fully GATE charge the gate of the upper ...
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... R N NTCEQ This gain, 1 DCR It is recommended to begin your droop design using the R NTC evaluation board available from Intersil. The gain of the droop amplifier circuit is expressed in Equation 15: (EQ droopamp After determining R (EQ. 10) Equation 16 to calculate the droop resistances R R DRP2 ...
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OCP + + − FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR CURRENT SENSING Following the evaluation board value and layout of NTC placement will minimize the engineering time. The current sensing traces should be routed directly ...
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... VID state and the output impedance is 8.0mΩ in order to achieve the 8.0mV/A load line highly recommended to design the compensation such that the regulator output impedance is 8.0mΩ. Intersil provides a spreadsheet to calculate the compensator parameters. Caution needs to be used in choosing the input resistor to the FB pin. Excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing through the FB pin ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 02/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 18 ISL6263B A ...