ISL6261CRZ Intersil, ISL6261CRZ Datasheet
ISL6261CRZ
Specifications of ISL6261CRZ
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ISL6261CRZ Summary of contents
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... TEMP PART RANGE PACKAGE PKG. MARKING (°C) (Pb-FREE) DWG. # ISL6261CRZ -10 to +100 40 Ld 6x6 L40.6x6 QFN ISL6261CRZ -10 to +100 40 Ld 6x6 L40.6x6 QFN, T&R ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7 QFN L48.7x7 QFN, T&R ISL6261IRZ -40 to +100 40 Ld 6x6 L40.6x6 QFN ...
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Pinouts FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB 1 PGOOD 2 FDE 3 PGD_IN RBIAS 4 VR_TT# 5 NTC 6 7 SOFT 8 OCSET VW 9 COMP ISL6261 ISL6261 (40 LD ...
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Absolute Maximum Ratings Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VIN. ...
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Electrical Specifications PARAMETER Error Amp Gain-Bandwidth Product (Note 3) Error Amp Slew Rate (Note 3) FB Input Current SOFT-START CURRENT Soft-start Current Soft Geyserville Current Soft Deeper Sleep Entry Current Soft Deeper Sleep Exit Current ...
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Electrical Specifications PARAMETER Leakage Current on VR_ON and PGD_IN Leakage Current on DPRSLPVR I I DAC(VID0-VID6), PSI# and DPRSTP# Input Low DAC(VID0-VID6), PSI# and DPRSTP# Input High Leakage Current of DAC(VID0- VID6) and DPRSTP# THERMAL ...
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Functional Pin Description FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB FDE Forced diode emulation enable signal. Logic high of FDE with logic low of DPRSTP# forces the ISL6261 to operate in diode emulation mode with an increased ...
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VSUM This pin is connected to one terminal of the capacitor in the current sensing R-C network. VIN Power stage input voltage used for input voltage feed forward to improve the input line transient performance. VSS Signal ground. ...
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Function Block Diagram FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261 8 ISL6261 FN9251.1 September 27, 2006 ...
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Simplified Application Circuit for DCR Current Sensing VR_TT# VID<0:6> DPRSTP# DPRSLPVR MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE FIGURE 2. ISL6261-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING 9 ISL6261 ...
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Simplified Application Circuit for Resistive Current Sensing VR_TT# VID<0:6> DPRSTP# DPRSLPVR MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE FIGURE 3. ISL6261-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING 10 ISL6261 +3.3 R ...
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... Implementation of diode emulation mode (DEM) operation further enhances system efficiency. The heart of the ISL6261 is the patented R Intersil’s Robust Ripple Regulator modulator. The R modulator combines the best features of fixed frequency and hysteretic PWM controllers while eliminating many of their shortcomings ...
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TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION VID6 VID5 VID4 VID3 VID2 VID1 ...
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TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 VID5 VID4 VID3 VID2 VID1 ...
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... DPRSLPVR logic. Intersil R High-speed input voltage transients have little effect on the output voltage. Intersil R transients to achieve fast response. Upon load application, the ISL6261 will transiently increase the switching frequency to deliver energy to the output more quickly. Compared with steady state operation, the PWM pulses during load application are generated earlier, which effectively increases the duty cycle and the response speed of the regulator ...
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Protection The ISL6261 provides overcurrent (OC), overvoltage (OV), undervoltage (UV) and over-temperature (OT) protections as shown in Table 3. Overcurrent is detected through the droop voltage, which is designed as described in the “Component Selection and Application” section. The OCSET ...
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OC Internal to DROOP ISL6261 1 1 VDIFF FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING ® given in the IMVP-6 specification, determines the choice of the SOFT capacitor through ...
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The Kelvin sense technique provides for extremely tight load line regulation at the processor die side. These traces should be laid out as noise sensitive traces. For optimum load line regulation performance, the traces connecting these two pins ...
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The NTC thermistor’s resistance is approximately given by the following formula: 1 ⋅ − ⋅ 273 NTC NTCTo T is the temperature of the NTC thermistor and b ...
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... NTC n . The choice par s droop independent of the inductor temperature desired to have where G network set to n temperature characteristics For different G1 and NTC thermistor preference, Intersil provides a design spreadsheet to generate the proper value (EQ. 16 ntc dcr R series R par ntc ntc series R n ...
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Figure 2) and R (R drp1 11 drp2 12 droop amplifier gain, according to Equation 22 drp droopamp R drp 1 After determining R and R networks, use Equation 23 to ...
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... It is highly recommended to design the compensation such that the regulator output impedance is 2.1mΩ. A type-III compensator is recommended to achieve the best performance. Intersil provides a spreadsheet to design the compensator parameters. Figure 13 shows an example of the spreadsheet. After the user inputs the parameters in the blue font, the spreadsheet will calculate ...
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ISL6261 FIGURE 13. AN EXAMPLE OF ISL6261 COMPENSATION SPREADSHEET 22 FN9251.1 September 27, 2006 ...
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OC Internal to DROOP ISL6261 1 FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) FIGURE 15. CCM EFFICIENCY, VID = 1.1V 8V, V ...
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Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V 8V 12.6V AND V IN1 IN2 FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V ...
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Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) 5V/div 0.2V/div 5V/div 10V/div FIGURE 25 VID 19V 2A, VID = 1.5V, BOOT IN Ch1: PGD_IN, Ch2: Vo, Ch3: CLK_EN#, Ch4: PHASE ...
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Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) FIGURE 31. C4 ENTRY/EXIT 12.6V 0.7A, IN HFM VID = 1.1V, LFM VID = 0.9V, C4 VID = 0.7625V, FDE = DPRSLPVR, Ch1: DPRSTP#, ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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ISL6261 Eval1 Rev. C Evaluation Board Schematic 100 R47 10K R42 10K R41 10K R40 10K R38 10K R37 10K R36 10K R32 P33 P31 P28 P27 P25 P24 P23 P20 P19 P18 P16 P13 OUT 10K R21 10K R18 ...
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ISL6261 Eval1 Rev. C Evaluation Board Schematic 22UF C64 22UF C58 22UF 330UF C52 C89 22UF 330UF C46 C41 22UF 330UF C36 C40 P41 P40 P39 P38 P37 56UF R83 56UF R82 C5B 10UF C5 10UF 10UF C4 1UF C32 ...
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ISL6261 Eval1 Rev. C Evaluation Board Schematic VSS AE4 VSS AE8 VSS AE11 VSS AE14 VSS AE16 VSS AE19 VSS AE23 VSS AE26 VSS AF3 VSS AF6 VSS AF8 VSS AF11 VSS AF13 VSS AF16 VSS AF19 VSS AF21 VSS ...
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ISL6261 Eval1 Rev. C Evaluation Board Schematic J11 J12 31 ISL6261 (Continued) 3 0.12 R76 0 R75 49.9K 3 R71 10UF C81 2 FN9251.1 September 27, 2006 ...
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ISL6261 Eval1 Rev. C Evaluation Board Schematic 1X3 10K R99 10K R96 10K R93 10K R90 10K R87 10K R84 10K R81 32 ISL6261 (Continued) BAV99 15PF C87 P45 ...
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Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 9/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 33 ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 9/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 34 ...