ISL6333CCRZ Intersil, ISL6333CCRZ Datasheet
ISL6333CCRZ
Specifications of ISL6333CCRZ
Available stocks
Related parts for ISL6333CCRZ
ISL6333CCRZ Summary of contents
Page 1
... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ...
Page 2
... ISL6333A IRZ ISL6333BCRZ* ISL6333B CRZ ISL6333BIRZ* ISL6333B IRZ ISL6333CCRZ* ISL6333C CRZ ISL6333CIRZ* ISL6333C IRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
Page 3
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Pinouts (Continued) 1 RSET 2 OFS VCC 5 6 REF 7 APA 8 COMP DVC IDROOP 11 VDIFF 12 RSET 1 OFS ...
Page 4
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Pinouts (Continued) 1 RSET 2 OFS VCC 5 REF 6 7 APA 8 COMP DVC CPURST_N 11 VDIFF 12 Controller Descriptions and Comments DIODE GATE ...
Page 5
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Integrated Driver Block Diagram PWM LOW POWER STATE SOFT-START AND FAULT LOGIC 5 LVCC SHOOT- GATE THROUGH CONTROL LOGIC PROTECTION UVCC BOOT UGATE 20kΩ PHASE 10kΩ LGATE FN6520.3 October 8, 2010 ...
Page 6
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333 OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 ...
Page 7
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333A OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 ...
Page 8
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333B OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 ...
Page 9
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333C OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 ...
Page 10
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333, ISL6333B VDIFF RGND DVC FB IDROOP COMP APA +5V VCC OFS FS REF ISL6333/B RGND IMON SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CPURST_N PSI# ...
Page 11
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333, ISL6333B with NTC Thermal Compensation VDIFF RGND DVC FB IDROOP COMP APA +5V VCC OFS FS REF ISL6333/B RGND IMON SS VID7 VID6 VID5 VID4 VID3 VID2 ...
Page 12
ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333A, ISL6333C VDIFF RGND DVC FB IDROOP COMP APA +5V VCC OFS FS REF ISL6333A RGND IMON SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CPURST_N PSI# ...
Page 13
... BOOT + 0.3V BOOT Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6333CRZ, ISL6333ACRZ, ISL6333BCRZ, ISL6333CCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6333IRZ, ISL6333AIRZ, ISL6333BIRZ, ISL6333CIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS ; EN = high ; EN = high ; EN = high ; EN = high ; EN = high = 100kΩ ...
Page 14
Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range. (Continued) PARAMETER Oscillator Ramp Amplitude, V (Note 3) P-P CONTROL THRESHOLDS EN Rising Threshold EN Hysteresis REFERENCE AND DAC System Accuracy (1.000V to 1.600V) System Accuracy (0.600V ...
Page 15
ISL6333, ISL6333A, ISL6333B, ISL6333C Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range. (Continued) PARAMETER Overvoltage Threshold During Soft-Start Overvoltage Threshold VR11, VSEN rising Overvoltage Hysteresis VSEN falling SWITCHING TIME (Note 3) UGATE Rise Time t ...
Page 16
ISL6333, ISL6333A, ISL6333B, ISL6333C Functional Pin Descriptions VCC VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor. PVCC1 (ISL6333, ISL6333B Only) This pin is ...
Page 17
ISL6333, ISL6333A, ISL6333B, ISL6333C RSET Connect this pin to VCC through a resistor to set the effective value of the internal R current sense resistors ISEN recommended a 0.1µF ceramic capacitor be placed in parallel with this resistor ...
Page 18
... FS pin. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal transitions high ...
Page 19
... FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION Adaptive Phase Alignment (APA) To further improve the transient response, the controllers also implement Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all of the channels together at the same time during large current step, high di/dt transient events. As Figure 3 shows, the APA ...
Page 20
... Channel current balance is achieved by comparing the sensed current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current-balance method is illustrated in Figure 4, with error correction for Channel 1 represented. In the figure, the cycle ...
Page 21
ISL6333, ISL6333A, ISL6333B, ISL6333C Continuous Current Sensing In order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. During this time the current-sense amplifier uses the ISEN inputs to reproduce a signal proportional to ...
Page 22
ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
Page 23
ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
Page 24
... DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the controllers to include the combined tolerances of each of these elements. ...
Page 25
ISL6333, ISL6333A, ISL6333B, ISL6333C In Equation 10 the reference voltage, V REF programmed offset voltage the total output current of OUT the converter the internal sense resistor connected ISEN to the ISEN+ pin, R ...
Page 26
ISL6333, ISL6333A, ISL6333B, ISL6333C Compensating Dynamic VID Transitions During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB ...
Page 27
ISL6333, ISL6333A, ISL6333B, ISL6333C . EXTERNAL CIRCUIT ISL6333, ISL6333B INTERNAL CIRCUIT PVCC1 +12V GVOT 1.0µF REG. BYP1 LVCC1 1.0µ F PVCC2_3 LVCC2, LVCC3 +12V 1.0µF UVCC1, UVCC2, PUVCC UVCC3 +5V TO +12V LVCC = LOWER GATE DRIVE 1.0µ F UVCC ...
Page 28
ISL6333, ISL6333A, ISL6333B, ISL6333C Upper MOSFET Gate Drive Voltage Versatility The controllers provide the user flexibility in choosing the upper MOSFET gate drive voltage for efficiency optimization. The controllers tie all the upper gate drive rails together to the PUVCC ...
Page 29
ISL6333, ISL6333A, ISL6333B, ISL6333C ramp times, t and t , can be calculated based Equations 20 and 21: 3 – ⋅ ⋅ ⋅ ( μ 1 – 3 ⋅ ...
Page 30
ISL6333, ISL6333A, ISL6333B, ISL6333C pulls the output voltage below a level that might cause damage to the load. The LGATE outputs remain high until VDIFF falls 110mV below the OVP threshold that tripped the overvoltage protection circuitry. The controllers will ...
Page 31
... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
Page 32
ISL6333, ISL6333A, ISL6333B, ISL6333C When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current ...
Page 33
ISL6333, ISL6333A, ISL6333B, ISL6333C The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated ...
Page 34
ISL6333, ISL6333A, ISL6333B, ISL6333C . ΔV 1 FIGURE 23. TIME CONSTANT MISMATCH BEHAVIOR Loadline Regulation Resistor If load line regulation is desired on the ISL6333 and ISL6333A, the IDROOP pin should be connected to the FB pin in order for ...
Page 35
ISL6333, ISL6333A, ISL6333B, ISL6333C In Equation 40 the per-channel filter inductance divided by the number of active channels the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter ...
Page 36
ISL6333, ISL6333A, ISL6333B, ISL6333C pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the ...
Page 37
ISL6333, ISL6333A, ISL6333B, ISL6333C enough to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. For a three-phase design, use Figure 27 to determine the ...
Page 38
ISL6333, ISL6333A, ISL6333B, ISL6333C DVC DVC DVC VDIFF VSEN IDROOP COMP R APA APA +5V VCC (CF1) R OFS OFS FS REF ...
Page 39
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
Page 40
ISL6333, ISL6333A, ISL6333B, ISL6333C Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 4/10 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL ...