EL7571CMZ Intersil, EL7571CMZ Datasheet - Page 7

• Manufacturer Part Number: EL7571CMZ
• Description: IC CTRLR PWM PROGRAMMABLE 20SOIC
• Manufacturer: Intersil

Specifications of EL7571CMZ

• Applications: Controller, Intel Pentium® II, Pro
• Voltage - Input: 4.5 ~ 12.6 V
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Applications Information
Circuit Description
General
The EL7571 is a fixed frequency, current mode, pulse width
modulated (PWM) controller with an integrated high
precision reference and a 5 bit Digital-to-Analog Converter
(DAC). The device incorporates all the active circuitry
required to implement a synchronous step down (buck)
converter which conforms to the Intel Pentium® II VRM
specification. Complementary switching outputs are
provided to drive dual NMOS power FET’s in either
synchronous or non-synchronous configurations, enabling
the user to realize a variety of high efficiency and low cost
converters.
Reference
A precision, temperature compensated band gap reference
forms the basis of the EL7571. The reference is trimmed
during manufacturing and provides 1% set point accuracy for
the overall regulator. AC rejection of the reference is
optimized using an external bypass capacitor C
Main Loop
A current mode PWM control loop is implemented in the
EL7571 (see block diagram). This configuration employs
dual feedback loops which provide both output voltage and
current feedback to the controller. The resulting system
offers several advantages over tradititional voltage control
systems, including simpler loop design, pulse by pulse
current limiting, rapid response to line variaion and good
load step response. Current feedback is performed by
sensing voltage across an external shunt resistor. Selection
of the shunt resistance value sets the level of current
feedback and thereby the load regulation and current limit
levels. Consequently, operation over a wide range of output
currents is possible. The reference output is fed to a 5 bit
DAC with step weighing conforming to the Intel VRM
Specification. Each DAC input includes an internal current
pull up which directly interfaces to the VID output of a
Pentium® II class microprocessor. The heart of the controller
is a triple-input direct summing differential comparator, which
sums voltage feedback, current feedback and compensating
ramp signals together. The relative gains of the comparator
input stages are weighed. The ratio of voltage feedback to
current feedback to compensating ramp defines the load
regulation and open loop voltage gain for the system,
respectively. The compensating ramp is required to maintain
large system signal system stability for PWM duty cycles
greater than 50%. Compensation ramp amplitude is user
adjustable and is set with a single external capacitor
(C
reset to ground whenever the high side drive signal is low. In
operation, the DAC output voltage is compared to the
regulator output, which has been internally attenuated. The
SLOPE
). The ramp voltage is ground referenced and is
7
REF
.
EL7571
resulting error voltage is compared with the compensating
ramp and current feedback voltage. PWM duty cycle is
adjusted by the comparator output such that the combined
comparator input sums to zero. A weighted comparator
scheme enhances system operation over traditional voltage
error amplifier loops by providing cycle-by-cycle adjustment
of the PWM output voltage, eliminating the need for error
amplifier compensation. The dominant pole in the loop is
defined by the output capacitance and equivalent load
resistance, the effect of the output inductor having been
canceled due to the current feedback. An output enable
(OUTEN) input allows the regulator output to be disabled by
an external logic control signal.
Auxiliary Comparators
The current feedback signal is monitored by two additional
comparators which set the operating limits for the main
inductor current. An over current comparator terminates the
PWM cycle independently of the main summing comparator
output whenever the voltage across the sense resistor
exceeds 154mV. For a 7.5mΩ resistor this corresponds to a
nominal 20A current limit. Since output current is
continuously monitored, cycle-by-cycle current limiting
results. A second comparator senses inductor current
reverse flow. The low side drive signal is terminated when
the sense resistor voltage is less than -5mV, corresponding
to a nominal reverse current of -0.67A, for a 7.5mΩ sense
resistor. Additionally, under fault conditions, with the
regulator output over-voltage, inductor current is prevented
from ramping to a high level in the reverse direction. This
prevents the parasitic boost action of the local power supply
when the fault is removed and potential damage to circuitry
connected to the local supply.
Oscillator
A system clock is generated by an internal relaxation
oscillator. Operating frequency is simple to adjust using a
single external capacitor C
discharge current in the oscillator is well defined and sets the
maximum duty cycle for the system at around 96%.
Soft-start
During start-up, potentially large currents can flow into the
regulator output capacitors due to the fast rate of change of
output voltage caused during start-up, although peak inrush
current will be limited by the over current comparator.
However an additionally internal switch capacitor soft-start
circuit controls the rate of change of output voltage during
start-up by overriding the voltage feedback input of the main
summing comparator, limiting the start-up ramp to around
1ms under typical operating conditions. The soft-start ramp
is reset whenever the output enable (OUTEN) is reset or
whenever the controller supply falls below 3.5V.
Watchdog
A system watchdog monitors the condition of the controller
supply and the integrity of the generated output voltage.
OSC
. The ratio of charge to