BD9778F-E2 Rohm Semiconductor, BD9778F-E2 Datasheet - Page 10

• Manufacturer Part Number: BD9778F-E2
• Description: IC REG SW 2A P-CH MOSF STDN SOP8
• Manufacturer: Rohm Semiconductor
• Type: Step-Down (Buck)r

Specifications of BD9778F-E2

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1 ~ 35 V
• Current - Output: 2A
• Frequency - Switching: 50kHz ~ 500kHz
• Voltage - Input: 7 ~ 35 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOP
• Power - Output: 690mW
• No. Of Outputs: 1
• Output Voltage: 35V
• Output Current: 2A
• Voltage Regulator Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 9778
• Input Voltage: 35 V
• Switching Frequency: 102 KHz
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: BD9778F-E2TR

* The set values listed above are all reference values. On the actual mounting of the IC, the characteristics may vary with the routing of wirings
and the types of parts in use. In this connection, it is recommended to thoroughly verify these values on the actual system prior to use.
5. Selection of input capacitor
4. Selection of diode
6. Setting of oscillation frequency
8. Setting of phase compensation (Rc and Cc)
Directions for pattern layout of PCB
Set diode rating with an adequate margin to the maximum load
an adequate margin to the maximum input voltage.
A diode with a low forward voltage and short reverse recovery
time will provide high efficiency.
Two capacitors, ceramic capacitor C
should be inserted between the V
a ceramic capacitor of 1 to 10 μF for the CThe capacitor C
should have a low ESR and a significantly large ripple current.
The ripple current I
by the following formula:
Select capacitors that can accept this ripple current.
If the capacitance of CIN and C is not optimum,
the IC may malfunction.
Referring Fig. 34 and Fig. 35 on the following page, select R
for the oscillation frequency to be used. Furthermore,
in order to eliminate noises, be sure to connect ceramic
capacitors of 0.1 to 1.0 μF in parallel.
The phase margin can be set through inserting a capacitor or
a capacitor and resistor between the INV pin and the FB pin.
Each set value varies with the output coil, capacitance,
I/O voltage, and load. Therefore, set the phase compensation
to the optimum value according to these conditions.
If this setting is not optimum, output oscillation may result.
current. Also, make setting of the rated inverse voltage with
(For details, refer to Application circuit on page 11.)
1
I
RMS
C
=I
O
× VO × (Vin-V
Cin
POWER
Fig.31
6
2
GND
RMS
Design procedure
can be obtained
R3
C3
BD9778HFP
L
Co
GND
O
Cx1
)/ V
8
IN
in
SIGNAL GND
R
L
O
A
D
and GND.Be sure to insert
IN
2
T
and bypass capacitor C,
R2
R1
C
T
5
3
8
Cx2
4
1
2
3
4
5
6
7
8
Arrange the wirings shown by heavy lines as short as possible
in a broad pattern.
Locate the input ceramic capacitor Cin as close to the VIN-GND pin
as possible.
Locate the R
Locate the R1 and R2 as close to the INV pin as possible,
and provide the shortest wiring from the R1 and R2 to the INV pin.
Locate the R1 and R2 as far away from the L as possible.
Separate POWER GND(Schottky diode, I/O capacitor's GND)
and SIGNAL GND(R
on SIGNAL GND at all.
Design the POWER wire line as wide and short as possible.
Additional pattern for Cx1 and Cx2 expand compesation flexibility.
10/16
When V
Select a diode of rated current of 2 A or more and rated
withstand voltage of 36 V or more.
When V
I
RMS
=1 × 5 × (13.2-5)/(13.2)
=0.485
IN
IN
T
and C
= 36 V and Io = (max.) 2 A,
= 13.2 V, Vo = 5 V, and Io = 1 A,
T
T
, C
as close to the GND pin as possible.
T
Calculation example
's GND), so that SW noise don't have an effect
2
I
RMS
=0.485A