AD9851/FSPCB Analog Devices Inc, AD9851/FSPCB Datasheet - Page 14

• Manufacturer Part Number: AD9851/FSPCB
• Description: BOARD EVAL FOR AD9851/FS
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9851/FSPCB

• Rohs Status: RoHS non-compliant
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9851/FS
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

the factory test mode. Exit from serial mode to parallel mode is
only possible using the RESET command.
The function assignments of the data and control words are shown
in Tables I and III; the detailed timing sequence for updating the
output frequency and/or phase, resetting the device, engaging the
6 REFCLK multiplier, and powering up/down, are shown in
the timing diagrams of Figures 13 through 20. As a programming
example for the following DDS characteristics:
1. Phase set to 11.25°
2. 6 REFCLK multiplier engaged
3. Powered-up mode selected
Word
W0
W1
W2
W3
W4
*This bit is always Logic 0 unless invoking the serial mode (see Figure 17). After serial mode is entered, this data bit must be set back to Logic 0 for proper operation.
Note: To update W0 it is not necessary to load W1 through W4. Simply load W0 and assert FQ_UD. To update W1, reload W0 then W1— users do not have random access to
programming words.
AD9851
Data[7]
Phase–b4 (MSB)
Freq–b31 (MSB)
Freq–b23
Freq–b15
Freq–b7
SYSCLK
W CLK
FQ UD
DATA
A
OUT
Data[6]
Phase–b3
Freq–b30
Freq–b22
Freq–b14
Freq–b6
Table I. 8-Bit Parallel-Load Data/Control Word Functional Assignment
Figure 13. Parallel Load Frequency/Phase UpdateTiming Sequence
*Specification does not apply when the 6 REFCLK multiplier is engaged.
*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD
Symbol
t
t
t
t
t
t
t
t
t
AND IS ASYNCHRONOUS WITH REFERENCE CLOCK
t
DS
DH
WH
WL
CD
FH
FL
FD
CF
DS
W0*
t
DH
Data[5]
Phase–b2
Freq–b29
Freq–b21
Freq–b13
Freq–b5
Definition
Data Setup Time
Data Hold Time
W_CLK High
W_CLK Low
REFCLK Delay after FQ_UD
FQ_UD High
FQ_UD Low
FQ_UD Delay after W_CLK
Output Latency from FQ_UD
Frequency Change
Phase Change
W1
Table II. Timing Specifications
t t t t t
FL
FL
FL
FL
FL
t
W2
WH
Data[4]
Phase–b1
Freq–b28
Freq–b20
Freq–b12
Freq–b4
t
WL
W3
–14–
Data[3]
Phase–b0 (LSB)
Freq–b27
Freq–b19
Freq–b11
Freq–b3
W4
4. Output = 10 MHz (for 180 MHz system clock)
In parallel mode, user would program the 40-bit control word
(composed of five 8-bit loads) as follows:
W0 = 00001001
W1 = 00001110
W2 = 00111000
W3 = 11100011
W4 = 10001110
If in serial mode, load the 40 bits starting from the LSB location
of W4 in the above array, loading from right to left, and ending
with the MSB of W0.
t
FD
t
CD
t t t t t t
FH
FH
FH
FH
FH
Min
3.5 ns
3.5 ns
3.5 ns
3.5 ns
3.5 ns*
7.0 ns
7.0 ns
7.0 ns
18 SYSCLK Cycles
13 SYSCLK Cycles
t t t t t
CF
CF
CF
CF
CF
CF
Data[2]
Power-Down
Freq–b26
Freq–b18
Freq–b10
Freq–b2
VALID DATA
Data[1]
Logic 0*
Freq–b25
Freq–b17
Freq–b9
Freq–b1
Data[0]
6 REFCLK
Multiplier
Freq–b24
Freq–b16
Freq–b8
Freq–b0 (LSB)
REV. D
Enable