AD9851/FSPCB Analog Devices Inc, AD9851/FSPCB Datasheet - Page 15

• Manufacturer Part Number: AD9851/FSPCB
• Description: BOARD EVAL FOR AD9851/FS
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9851/FSPCB

• Rohs Status: RoHS non-compliant
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9851/FS
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Note: The timing diagram above shows the minimal amount of reset time needed before writing to the device. However, the master reset does not have to be synchronous to
the SYSCLK if the minimal time is not required.
Results of Reset, Figure 14
– Phase accumulator zeroed such that the output = 0 Hz (dc)
– Phase offset register set to 0 such that DAC IOUT = full-scale
– Internal programming address pointer reset to W0
– Power-down bit reset to 0 (power-down disabled)
– 40-bit data input register is NOT cleared
– 6 reference clock multiplier is disabled
– Parallel programming mode selected by default
REV. D
DATA (W0)
DATA (W0)
output and IOUTB = zero mA output
STROBE
SYSCLK
SYSCLK
W CLK
FQ UD
W CLK
FQ UD
DAC
Figure 15. Parallel Load Power-Down Sequence/
Internal Operation
Figure 16. Parallel Load Power-Up Sequence (to
Recover from Power-Down)/Internal Operation
INTERNAL CLOCKS
XXXXX00X
XXXXX10X
ENABLED
SYSCLK
RESET
A
OUT
SYMBOL
t
t
t
t
t
*SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS TO THE SYSCLK IF THE MINIMAL TIME IS NOT REQUIRED.
RH
RL
RR
RS
OL
t
RH
INTERNAL CLOCKS
DISABLED
Figure 14. Master ResetTiming Sequence
CLK DELAY AFTER RESET RISING EDGE 3.5ns
RESET FALLING EDGE AFTER CLK
MINIMUM RESET WIDTH
RESET OUTPUT LATENCY
RECOVERY FROM RESET
DEFINITION
t
RS
–15–
t
OL
Entry to the serial mode, see Figure 17, is via the parallel mode,
which is selected by default after a RESET is asserted. One needs
only to program the first eight bits (word W0) with the sequence
xxxxx011 as shown in Figure 17 to change from parallel to serial
mode. The W0 programming word may be sent over the 8-bit
data bus or hardwired as shown in Figure 18. After serial mode
is achieved, the user must follow the programming sequence of
Figure 19.
Note: After serial mode is invoked, it is best to immediately write
a valid 40-bit serial word (see Figure 19), even if it is all zeros,
followed by a FQ_UD rising edge to flush the residual data left in
the DDS core. A valid 40-bit serial word is any word where W33
is Logic 0.
DATA (W0)
W CLK
FQ UD
Figure 18. Hardwired xxxxx011 Configuration for
Serial Load Enable Word W0 in Figure 17
t
RL
Figure 17. Serial Load Enable Sequence
t
SUPPLY
RR
3.5ns
5 SYSCLK CYCLES
13 SYSCLK CYCLES
2 SYSCLK CYCLES
+V
*
*
MIN SPEC
10k
COS (0  )
XXXXX011
1
2
3
4
D3
D2
D1
D0
AD9851
ENABLE
SERIAL MODE
AD9851
D4
D5
D6
D7
28
27
26
25