AD9851/FSPCB Analog Devices Inc, AD9851/FSPCB Datasheet - Page 18

• Manufacturer Part Number: AD9851/FSPCB
• Description: BOARD EVAL FOR AD9851/FS
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9851/FSPCB

• Rohs Status: RoHS non-compliant
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9851/FS
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Apply power to AD9851 evaluation board. The AD9851 is pow-
ered separately from the other active components on the board
via connector marked DUT +V. The connector marked 5 V is
used to power the CMOS latches, optional crystal oscillator and
pull-up resistors. Both 5 V and DUT +V may be tied together for
ease of operation without adverse affects. The AD9851 may be
powered with 2.7 V to 5.25 V.
Connect an external 50  Z clock source or remove R2 and
install a suitable crystal clock oscillator with CMOS output levels
at Y1. A sine wave signal generator may be used as a clock source
at frequencies >50 MHz by dc offsetting the output signal to
1/2 the supply voltage to the AD9851. This method requires a
minimum of 2 V p-p signal and disabling of the 6 REFCLK
Multiplier function.
Locate the file called WIN9851.EXE and execute that program.
The computer monitor should show a control panel that allows
operation of the AD9851 evaluation board by use of a mouse.
Operation
On the control panel locate the box labeled COMPUTER I/O.
Click the correct parallel printer port for the host computer
and then click the TEST box. A message will appear indicating
whether the selection of output port is correct. Choose other
ports as necessary to achieve a correct port setting.
Click the MASTER RESET button. This will reset the part to
0 Hz, 0° phase, parallel programming mode. The output from the
DAC IOUT should be a dc voltage equal to the full-scale output
of the AD9851 (1 V for the AD9851/CGPCB and 0.5 V for the
AD9851/FSPCB), while the DAC IOUTB should be 0 V for both
evaluation boards. RESET should always be the first command to the
AD9851 following power-up.
Locate the CLOCK SECTION and place the cursor in the
FREQUENCY box. Enter the clock frequency (in MHz) that
will be applied to the reference clock input of the AD9851.
Click the PLL box in the CONTROL FUNCTION menu if the
6 reference clock multiplier is to be engaged —a check mark
will appear when engaged. When the reference clock multiplier
is engaged, software will multiply the value entered in the fre-
quency box by 6; otherwise, the value entered is the value used.
Click the LOAD button or press the enter key.
Move the cursor to the OUTPUT FREQUENCY box and type
in the desired frequency (in MHz). Click the LOAD button or
press the enter key. The BUS MONITOR section of the control
panel will show the 32-bit frequency word and 8-bit phase/
control word. Upon completion of this step, the AD9851 output
should be active at the programmed frequency/phase.
Changing the output phase is accomplished by clicking the down
arrow in the OUTPUT PHASE DELAY box to make a selection
and then clicking the LOAD button. Note: clicking the load but-
tons of the clock frequency box, the output frequency box, or the
phase box will automatically initiate a reloading of all three boxes
and issuance of a FQ_UD (frequency update) pulse. To bypass
this automatic reloading and frequency update sequence, refer to
the note below.
AD9851
–18–
Other operational modes (Frequency Sweeping, Sleep, Serial
Input) are available. Frequency sweeping allows the user to
enter a start and stop frequency and to specify the frequency
step size. Sweeping begins at the start frequency, proceeds to
the stop frequency in a linear manner, reverses direction, and
sweeps back to the start frequency repeatedly.
Note: For those who may be operating multiple AD9851 eval-
uation boards from one computer, a MANUAL FREQUENCY
UPDATE option exists. By eliminating the automatic issuance
of an FQ_UD, the user can load the 40-bit input registers of
multiple AD9851s without transferring that data to the inter-
nal accumulators. When all input registers are loaded, a single
FREQUENCY UPDATE pulse can be issued to all AD9851s.
A block diagram of this technique is shown in the AD9851 data
sheet as a quadrature oscillator application. This single pulse
synchronizes all the units so that their particular phases and
frequencies take effect simultaneously. Proper synchronization
requires that each AD9851 be clocked by the same reference
clock source and that each oscillator be in an identical state while
being programmed. RESET command ensures identical states.
When manual frequency update is selected, a new box labeled
FREQUENCY UPDATE will appear just above the frequency
sweeping menu. Clicking the box initiates a single FQ_UD pulse.
Note: RESET can be used to synchronize multiple oscillators.
If several oscillators have already been programmed at various
phases or frequencies, issuance of a RESET pulse will set their
outputs to 0 Hz and 0 phase. By issuing a common FQ_UD, the
previously programmed information in the 40-bit input registers
will transfer once again to the DDS core and take effect in 18
clock cycles. This is due to the fact that RESET does not affect
the contents of the 40-bit input register in any way.
The AD9851/FSPCB provides access into and out of the on-chip
comparator via test point pairs (each pair has an active input and
a ground connection). The two active inputs are labeled TP1
and TP2. The unmarked hole next to each labeled test point is a
ground connection. The two active outputs are labeled TP5 and
TP6. Adjacent to those test points are unmarked ground connec-
tions. To prevent unwanted comparator chatter when not in use,
the two inputs are pulled either to ground or +V via 1 k resistors.
The AD9851/CGPCB provides BNC inputs and outputs asso-
ciated with the on-chip comparator and an onboard, 7th order,
200  input /output Z, elliptic 70 MHz low-pass filter. Jumper-
ing (soldering a wire) E1 to E2, E3 to E4, and E5 to E6 connects
the onboard filter and the midpoint switching voltage to the
comparator. Users may elect to insert their own filter and com-
parator threshold voltage by removing the jumpers and inserting
a filter between J7 and J6 and providing a comparator threshold
voltage at E1.
Use of the XTAL oscillator socket on the evaluation board to sup-
ply the clock to the AD9851 requires the removal R2 (a 50  chip
resistor) unless the oscillator can drive a 50  load. The crystal
oscillator should be either TTL or CMOS (preferably) compatible.
REV. D