DS50EV401-EVK National Semiconductor, DS50EV401-EVK Datasheet - Page 2

• Manufacturer Part Number: DS50EV401-EVK
• Description: KIT EVAL DS50EV401 EQUALIZER
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50EV401-EVK

• Main Purpose: Interface, Cable Equalizer
• Utilized Ic / Part: DS50EV401
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0-
IN_1+
IN_1-
IN_2+
IN_2-
IN_3+
IN_3-
OUT_0+
OUT_0-
OUT_1+
OUT_1-
OUT_2+
OUT_2-
OUT_3+
OUT_3-
EQUALIZATION CONTROL
MODE
DEVICE CONTROL
EN0
EN1
EN2
EN3
SD0
SD1
SD2
SD3
Pin Name
Pin Descriptions
Pin Number
11
12
36
35
33
32
29
28
26
25
14
44
42
40
38
45
43
41
39
1
2
4
5
8
9
O, LVCMOS Channel 0 Signal Detect Output Pin
O, LVCMOS Channel 1 Signal Detect Output Pin
O, LVCMOS Channel 2 Signal Detect Output Pin
O, LVCMOS Channel 3 Signal Detect Output Pin
I, LVCMOS MODE selects the equalizer frequency for EQ channels. MODE is internally pulled low.
I, LVCMOS Channel 0 Enable Input Pin
I, LVCMOS Channel 1 Enable Input Pin
I, LVCMOS Channel 2 Enable Input Pin
I, LVCMOS Channel 3 Enable Input Pin
I/O, Type
O, CML
O, CML
O, CML
O, CML
I, CML
I, CML
I, CML
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_0+ to VDD and IN_0- to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_1+ to VDD and IN_1- to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_2+ to VDD and IN_2- to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_3+ to VDD and IN_3- to VDD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to V
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to V
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to V
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to V
Pin is internally pulled High.
Pin is internally pulled High.
Pin is internally pulled High.
Pin is internally pulled High.
L = 6.0 - 8.0 Gbps setting
H = 2.5 Gbps / 5.0 Gbps setting
H = normal operation (enabled)
L = standby mode
H = normal operation (enabled)
L = standby mode
H = normal operation (enabled)
L = standby mode
H = normal operation (enabled)
L = standby mode
H = signal detected
L = no signal detected
H = signal detected
L = no signal detected
H = signal detected
L = no signal detected.
H = signal detected
L = no signal detected
2
Description
DD
DD
DD
DD
and OUT_0- to V
and OUT_1- to V
and OUT_2- to V
and OUT_3- to V
DD
DD
DD
DD
.
.
.
.