DS50EV401-EVK National Semiconductor, DS50EV401-EVK Datasheet - Page 8

• Manufacturer Part Number: DS50EV401-EVK
• Description: KIT EVAL DS50EV401 EQUALIZER
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50EV401-EVK

• Main Purpose: Interface, Cable Equalizer
• Utilized Ic / Part: DS50EV401
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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Functional Description
DS50EV401 APPLICATIONS INFORMATION
The DS50EV401 is a programmable quad equalizer opti-
mized for copper backplanes and cables at transmission rates
of 2.5 Gbps up to 8 Gbps. The device consists of an input
receive equalizer followed by a limiting amplifier. The equal-
izer is designed to open an input eye that is completely closed
due to inter-symbol interference (ISI) induced by the channel
Data Channels
The DS50EV401 consists of four data channels. Each chan-
nel provides input termination, receiver equalization, signal
limiting, offset cancellation, and a CML output driver, as
shown in
equalization, controlled by the pin MODE. The equalization
levels are set simultaneously on all 4 channels, as described
in
When an idle condition is sensed on a channel’s input, the
transmit driver is automatically placed into electrical idle
6 mil microstrip FR4
Table
trace length (in)
1.
Figure
0–30
0–40
6. The data channels support two levels of
24 AWG Twin-AX cable
length (m)
0–10
0–7
FIGURE 6. General Block Diagram
TABLE 1. MODE Control Table
Frequency
2.5 Gbps
5.0 Gbps
8 Gbps
8
interconnect. The equalization is set to keep residual deter-
ministic jitter below 0.2 unit intervals (UI) regardless of data
rate. This equalization scheme allows one equalization set-
ting to satisfy most serial links between 2.5 and 5.0 Gbps. The
DS50EV401 is intended as a unidirectional receiver that
should be placed in close physical proximity to the link end
point. Therefore the transmitter does not include de-emphasis
as TX equalization would not be needed over the short dis-
tance between the equalizer and the end point.
mode. The common mode voltage is set, and the differential
output is forced to zero. To save power, the output driver cur-
rent is powered off when the device is in electrical idle mode.
All other circuits maintain their bias currents allowing a fast
recovery from idle to the active state. Electric idle is performed
on a per channel basis, and several channels can be in idle
while others are actively passing data.
Channel Loss
16 dB
14 dB
20 dB
MODE
0
1
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